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net: stmmac: spelling corrections
Correct spelling as flagged by codespell. Signed-off-by: Simon Horman <horms@kernel.org> Reviewed-by: Joe Damato <joe@dama.to> Link: https://patch.msgid.link/20260129-stmmac-spell-v1-1-c7df9a96e482@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Simon Horman
Jakub Kicinski
parent
43dc088c19
commit
96e1c895b5
10 changed files with 17 additions and 17 deletions
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@ -270,9 +270,9 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
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if (of_machine_is_compatible("fsl,imx8mp") ||
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of_machine_is_compatible("fsl,imx91") ||
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of_machine_is_compatible("fsl,imx93")) {
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/* Binding doc describes the propety:
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/* Binding doc describes the property:
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* is required by i.MX8MP, i.MX91, i.MX93.
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* is optinoal for i.MX8DXL.
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* is optional for i.MX8DXL.
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*/
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dwmac->intf_regmap =
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syscon_regmap_lookup_by_phandle_args(np, "intf_mode", 1,
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@ -746,7 +746,7 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
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v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
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writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
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/* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
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/* The timeout was previously set to 10ms, but some board (OrangePI0)
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* need more if no cable plugged. 100ms seems OK
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*/
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err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
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@ -821,7 +821,7 @@ static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
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return ret;
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}
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/* Make sure the EPHY is properly reseted, as U-Boot may leave
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/* Make sure the EPHY is properly reset, as U-Boot may leave
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* it at deasserted state, and thus it may fail to reset EMAC.
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*
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* This assumes the driver has exclusive access to the EPHY reset.
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@ -152,7 +152,7 @@ enum inter_frame_gap {
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/*--- DMA BLOCK defines ---*/
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/* DMA Bus Mode register defines */
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/* Programmable burst length (passed thorugh platform)*/
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/* Programmable burst length (passed through platform)*/
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#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */
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#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
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@ -108,7 +108,7 @@ static void dwmac100_set_filter(struct mac_device_info *hw,
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memset(mc_filter, 0, sizeof(mc_filter));
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netdev_for_each_mc_addr(ha, dev) {
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/* The upper 6 bits of the calculated CRC are used to
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* index the contens of the hash table
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* index the contents of the hash table
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*/
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int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
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/* The most significant bit determines the register to
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@ -88,7 +88,7 @@ static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
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/* bits 5 7 0 | Frame status
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* ----------------------------------------------------------
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* 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
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* 0 0 0 | IEEE 802.3 Type frame (length < 1536 octets)
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* 1 0 0 | IPv4/6 No CSUM errorS.
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* 1 0 1 | IPv4/6 CSUM PAYLOAD error
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* 1 1 0 | IPv4/6 CSUM IP HR error
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@ -252,7 +252,7 @@ static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
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writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
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}
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/* This reads the MAC core counters (if actaully supported).
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/* This reads the MAC core counters (if actually supported).
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* by default the MMC core is programmed to reset each
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* counter after a read. So all the field of the mmc struct
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* have to be incremented.
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@ -420,7 +420,7 @@ static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)
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*dest = *dest + tmp;
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}
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/* This reads the MAC core counters (if actaully supported).
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/* This reads the MAC core counters (if actually supported).
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* by default the MMC core is programmed to reset each
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* counter after a read. So all the field of the mmc struct
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* have to be incremented.
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@ -43,7 +43,7 @@ static void config_sub_second_increment(void __iomem *ioaddr,
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unsigned long data;
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u32 reg_value;
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/* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second
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/* For GMAC3.x, 4.x versions, in "fine adjustment mode" set sub-second
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* increment to twice the number of nanoseconds of a clock cycle.
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* The calculation of the default_addend value by the caller will set it
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* to mid-range = 2^31 when the remainder of this division is zero,
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@ -1130,7 +1130,7 @@ static int stmmac_mac_enable_tx_lpi(struct phylink_config *config, u32 timer,
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stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
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STMMAC_DEFAULT_TWT_LS);
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/* Try to cnfigure the hardware timer. */
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/* Try to configure the hardware timer. */
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ret = stmmac_set_lpi_mode(priv, priv->hw, STMMAC_LPI_TIMER,
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priv->tx_lpi_clk_stop, priv->tx_lpi_timer);
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@ -3511,7 +3511,7 @@ static void stmmac_mac_config_rss(struct stmmac_priv *priv)
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/**
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* stmmac_mtl_configuration - Configure MTL
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* @priv: driver private structure
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* Description: It is used for configurring MTL
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* Description: It is used for configuring MTL
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*/
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static void stmmac_mtl_configuration(struct stmmac_priv *priv)
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{
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@ -4389,7 +4389,7 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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/* Always insert VLAN tag to SKB payload for TSO frames.
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*
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* Never insert VLAN tag by HW, since segments splited by
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* Never insert VLAN tag by HW, since segments split by
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* TSO engine will be un-tagged by mistake.
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*/
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if (skb_vlan_tag_present(skb)) {
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@ -5962,7 +5962,7 @@ static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
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unsigned long flags;
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spin_lock_irqsave(&ch->lock, flags);
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/* Both RX and TX work done are compelte,
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/* Both RX and TX work done are complete,
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* so enable both RX & TX IRQs.
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*/
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stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
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@ -6294,7 +6294,7 @@ static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
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/**
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* stmmac_ioctl - Entry point for the Ioctl
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* @dev: Device pointer.
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* @rq: An IOCTL specefic structure, that can contain a pointer to
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* @rq: An IOCTL specific structure, that can contain a pointer to
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* a proprietary structure used to pass information to the driver.
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* @cmd: IOCTL command
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* Description:
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@ -483,7 +483,7 @@ void stmmac_pcs_clean(struct net_device *ndev)
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* If a specific clk_csr value is passed from the platform
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* this means that the CSR Clock Range selection cannot be
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* changed at run-time and it is fixed (as reported in the driver
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* documentation). Viceversa the driver will try to set the MDC
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* documentation). Vice versa the driver will try to set the MDC
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* clock dynamically according to the actual clock input.
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*/
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static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)
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@ -2000,7 +2000,7 @@ void stmmac_selftest_run(struct net_device *dev,
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}
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/*
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* First tests will always be MAC / PHY loobpack. If any of
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* First tests will always be MAC / PHY loopback. If any of
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* them is not supported we abort earlier.
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*/
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if (ret) {
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