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Merge tag 'drm-intel-gt-next-2026-01-16' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

Browse source 
Driver Changes:

- Bump recommended GuC version for DG2 and MTL
- Fix for syzkaller found NULL deref in execbuf (Krzyssztof, Gangmin)

- Use designated initializers in debugfs code (Sebastian)
- Selftest and static checker fixes (Ard, Sk)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patch.msgid.link/aWnzOx78S4Vh38QE@jlahtine-mobl
This commit is contained in:
Dave Airlie 2026-01-19 13:51:08 +10:00
commit 95adee9a04
12 changed files with 75 additions and 52 deletions
Download patch file Download diff file Expand all files Collapse all files

37
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
View file

@ -951,13 +951,13 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
vma = eb_lookup_vma(eb, eb->exec[i].handle);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto err;
return err;
}
err = eb_validate_vma(eb, &eb->exec[i], vma);
if (unlikely(err)) {
i915_vma_put(vma);
goto err;
return err;
}
err = eb_add_vma(eb, &current_batch, i, vma);
@ -966,19 +966,8 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
if (i915_gem_object_is_userptr(vma->obj)) {
err = i915_gem_object_userptr_submit_init(vma->obj);
if (err) {
if (i + 1 < eb->buffer_count) {
/*
* Execbuffer code expects last vma entry to be NULL,
* since we already initialized this entry,
* set the next value to NULL or we mess up
* cleanup handling.
*/
eb->vma[i + 1].vma = NULL;
}
if (err)
return err;
}
eb->vma[i].flags |= __EXEC_OBJECT_USERPTR_INIT;
eb->args->flags |= __EXEC_USERPTR_USED;
@ -986,10 +975,6 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
}
return 0;
err:
eb->vma[i].vma = NULL;
return err;
}
static int eb_lock_vmas(struct i915_execbuffer *eb)
@ -3375,7 +3360,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
eb.exec = exec;
eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
eb.vma[0].vma = NULL;
memset(eb.vma, 0, (args->buffer_count + 1) * sizeof(struct eb_vma));
eb.batch_pool = NULL;
eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
@ -3584,7 +3570,18 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
if (err)
return err;
/* Allocate extra slots for use by the command parser */
/*
* Allocate extra slots for use by the command parser.
*
* Note that this allocation handles two different arrays (the
* exec2_list array, and the eventual eb.vma array introduced in
* i915_gem_do_execbuffer()), that reside in virtually contiguous
* memory. Also note that the allocation intentionally doesn't fill the
* area with zeros, because the exec2_list part doesn't need to be, as
* it's immediately overwritten by user data a few lines below.
* However, the eb.vma part is explicitly zeroed later in
* i915_gem_do_execbuffer().
*/
exec2_list = kvmalloc_array(count + 2, eb_element_size(),
__GFP_NOWARN | GFP_KERNEL);
if (exec2_list == NULL) {

4
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
View file

@ -75,8 +75,8 @@ DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(steering);
static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "reset", &reset_fops, NULL },
{ "steering", &steering_fops },
{ .name = "reset", .fops = &reset_fops },
{ .name = "steering", .fops = &steering_fops },
};
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);

2
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
View file

@ -29,7 +29,7 @@ DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(engines);
void intel_gt_engines_debugfs_register(struct intel_gt *gt, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "engines", &engines_fops },
{ .name = "engines", .fops = &engines_fops },
};
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);

15
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
View file

@ -588,13 +588,14 @@ DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "drpc", &drpc_fops, NULL },
{ "frequency", &frequency_fops, NULL },
{ "forcewake", &fw_domains_fops, NULL },
{ "forcewake_user", &forcewake_user_fops, NULL},
{ "llc", &llc_fops, llc_eval },
{ "rps_boost", &rps_boost_fops, rps_eval },
{ "perf_limit_reasons", &perf_limit_reasons_fops, perf_limit_reasons_eval },
{ .name = "drpc", .fops = &drpc_fops },
{ .name = "frequency", .fops = &frequency_fops },
{ .name = "forcewake", .fops = &fw_domains_fops },
{ .name = "forcewake_user", .fops = &forcewake_user_fops},
{ .name = "llc", .fops = &llc_fops, .eval = llc_eval },
{ .name = "rps_boost", .fops = &rps_boost_fops, .eval = rps_eval },
{ .name = "perf_limit_reasons", .fops = &perf_limit_reasons_fops,
.eval = perf_limit_reasons_eval },
};
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);

4
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
View file

@ -293,8 +293,8 @@ DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_topology);
void intel_sseu_debugfs_register(struct intel_gt *gt, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "sseu_status", &sseu_status_fops, NULL },
{ "sseu_topology", &sseu_topology_fops, NULL },
{ .name = "sseu_status", .fops = &sseu_status_fops },
{ .name = "sseu_topology", .fops = &sseu_topology_fops },
};
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);

34
drivers/gpu/drm/i915/gt/selftest_rps.c
View file

@ -378,6 +378,7 @@ int live_rps_control(void *arg)
enum intel_engine_id id;
struct igt_spinner spin;
intel_wakeref_t wakeref;
u32 throttle;
int err = 0;
/*
@ -463,6 +464,9 @@ int live_rps_control(void *arg)
max = rps_set_check(rps, limit);
max_dt = ktime_sub(ktime_get(), max_dt);
throttle = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
throttle &= GT0_PERF_LIMIT_REASONS_MASK;
min_dt = ktime_get();
min = rps_set_check(rps, rps->min_freq);
min_dt = ktime_sub(ktime_get(), min_dt);
@ -478,11 +482,9 @@ int live_rps_control(void *arg)
min, max, ktime_to_ns(min_dt), ktime_to_ns(max_dt));
if (limit != rps->max_freq) {
u32 throttle = intel_uncore_read(gt->uncore,
intel_gt_perf_limit_reasons_reg(gt));
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
engine->name, throttle & GT0_PERF_LIMIT_REASONS_MASK);
if (throttle)
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
engine->name, throttle);
show_pstate_limits(rps);
}
@ -1138,6 +1140,7 @@ int live_rps_power(void *arg)
struct intel_engine_cs *engine;
enum intel_engine_id id;
struct igt_spinner spin;
u32 throttle;
int err = 0;
/*
@ -1195,6 +1198,9 @@ int live_rps_power(void *arg)
max.freq = rps->max_freq;
max.power = measure_power_at(rps, &max.freq);
throttle = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
throttle &= GT0_PERF_LIMIT_REASONS_MASK;
min.freq = rps->min_freq;
min.power = measure_power_at(rps, &min.freq);
@ -1210,12 +1216,21 @@ int live_rps_power(void *arg)
pr_notice("Could not control frequency, ran at [%d:%uMHz, %d:%uMhz]\n",
min.freq, intel_gpu_freq(rps, min.freq),
max.freq, intel_gpu_freq(rps, max.freq));
if (throttle)
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
engine->name, throttle);
continue;
}
if (11 * min.power > 10 * max.power) {
pr_err("%s: did not conserve power when setting lower frequency!\n",
engine->name);
if (throttle)
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
engine->name, throttle);
err = -EINVAL;
break;
}
@ -1241,6 +1256,7 @@ int live_rps_dynamic(void *arg)
struct intel_engine_cs *engine;
enum intel_engine_id id;
struct igt_spinner spin;
u32 throttle;
int err = 0;
/*
@ -1293,6 +1309,9 @@ int live_rps_dynamic(void *arg)
max.freq = wait_for_freq(rps, rps->max_freq, 500);
max.dt = ktime_sub(ktime_get(), max.dt);
throttle = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
throttle &= GT0_PERF_LIMIT_REASONS_MASK;
igt_spinner_end(&spin);
min.dt = ktime_get();
@ -1308,6 +1327,11 @@ int live_rps_dynamic(void *arg)
if (min.freq >= max.freq) {
pr_err("%s: dynamic reclocking of spinner failed\n!",
engine->name);
if (throttle)
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
engine->name, throttle);
err = -EINVAL;
}

2
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c
View file

@ -29,7 +29,7 @@ DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(gsc_info);
void intel_gsc_uc_debugfs_register(struct intel_gsc_uc *gsc_uc, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "gsc_info", &gsc_info_fops, NULL },
{ .name = "gsc_info", .fops = &gsc_info_fops },
};
if (!intel_gsc_uc_is_supported(gsc_uc))

13
drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
View file

@ -132,12 +132,13 @@ DEFINE_SIMPLE_ATTRIBUTE(guc_sched_disable_gucid_threshold_fops,
void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "guc_info", &guc_info_fops, NULL },
{ "guc_registered_contexts", &guc_registered_contexts_fops, NULL },
{ "guc_slpc_info", &guc_slpc_info_fops, &intel_eval_slpc_support},
{ "guc_sched_disable_delay_ms", &guc_sched_disable_delay_ms_fops, NULL },
{ "guc_sched_disable_gucid_threshold", &guc_sched_disable_gucid_threshold_fops,
NULL },
{ .name = "guc_info", .fops = &guc_info_fops },
{ .name = "guc_registered_contexts", .fops = &guc_registered_contexts_fops },
{ .name = "guc_slpc_info", .fops = &guc_slpc_info_fops,
.eval = intel_eval_slpc_support },
{ .name = "guc_sched_disable_delay_ms", .fops = &guc_sched_disable_delay_ms_fops },
{ .name = "guc_sched_disable_gucid_threshold",
.fops = &guc_sched_disable_gucid_threshold_fops },
};
if (!intel_guc_is_supported(guc))

8
drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
View file

@ -162,10 +162,10 @@ void intel_guc_log_debugfs_register(struct intel_guc_log *log,
struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "guc_log_dump", &guc_log_dump_fops, NULL },
{ "guc_load_err_log_dump", &guc_load_err_log_dump_fops, NULL },
{ "guc_log_level", &guc_log_level_fops, NULL },
{ "guc_log_relay", &guc_log_relay_fops, NULL },
{ .name = "guc_log_dump", .fops = &guc_log_dump_fops },
{ .name = "guc_load_err_log_dump", .fops = &guc_load_err_log_dump_fops},
{ .name = "guc_log_level", .fops = &guc_log_level_fops },
{ .name = "guc_log_relay", .fops = &guc_log_relay_fops },
};
if (!intel_guc_is_supported(log_to_guc(log)))

2
drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c
View file

@ -26,7 +26,7 @@ DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(huc_info);
void intel_huc_debugfs_register(struct intel_huc *huc, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "huc_info", &huc_info_fops, NULL },
{ .name = "huc_info", .fops = &huc_info_fops },
};
if (!intel_huc_is_supported(huc))

2
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
View file

@ -40,7 +40,7 @@ DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(uc_usage);
void intel_uc_debugfs_register(struct intel_uc *uc, struct dentry *gt_root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "usage", &uc_usage_fops, NULL },
{ .name = "usage", .fops = &uc_usage_fops },
};
struct dentry *root;

4
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
View file

@ -88,8 +88,8 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* security fixes, etc. to be enabled.
*/
#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
fw_def(METEORLAKE, 0, guc_maj(mtl, 70, 12, 1)) \
fw_def(DG2, 0, guc_maj(dg2, 70, 12, 1)) \
fw_def(METEORLAKE, 0, guc_maj(mtl, 70, 53, 0)) \
fw_def(DG2, 0, guc_maj(dg2, 70, 53, 0)) \
fw_def(ALDERLAKE_P, 0, guc_maj(adlp, 70, 12, 1)) \
fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \
fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \