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drm/i915/pch: convert intel_pch_refclk.c to struct intel_display
Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_pch_refclk.[ch] to struct intel_display. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/1bf35f05dc921e0ca548b0d0d8d7f5b7098e8140.1742554320.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
parent
ca2f596a67
commit
93e7a4c716
7 changed files with 85 additions and 81 deletions
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@ -7815,7 +7815,7 @@ void intel_setup_outputs(struct intel_display *display)
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intel_encoder_possible_clones(encoder);
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}
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intel_init_pch_refclk(dev_priv);
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intel_init_pch_refclk(display);
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drm_helper_move_panel_connectors_to_head(display->drm);
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}
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@ -1373,18 +1373,18 @@ static void hsw_enable_pc8(struct intel_display *display)
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intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
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PCH_LP_PARTITION_LEVEL_DISABLE, 0);
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lpt_disable_clkout_dp(dev_priv);
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lpt_disable_clkout_dp(display);
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hsw_disable_lcpll(display, true, true);
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}
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static void hsw_disable_pc8(struct intel_display *display)
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{
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struct drm_i915_private *dev_priv = to_i915(display->drm);
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struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
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drm_dbg_kms(display->drm, "Disabling package C8+\n");
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hsw_restore_lcpll(display);
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intel_init_pch_refclk(dev_priv);
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intel_init_pch_refclk(display);
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/* Many display registers don't survive PC8+ */
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#ifdef I915 /* FIXME */
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@ -715,7 +715,6 @@ static void hsw_ddi_spll_enable(struct intel_display *display,
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static void hsw_ddi_wrpll_disable(struct intel_display *display,
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struct intel_shared_dpll *pll)
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{
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struct drm_i915_private *i915 = to_i915(display->drm);
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const enum intel_dpll_id id = pll->info->id;
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intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
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@ -726,13 +725,12 @@ static void hsw_ddi_wrpll_disable(struct intel_display *display,
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* that depend on it have been shut down.
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*/
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if (display->dpll.pch_ssc_use & BIT(id))
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intel_init_pch_refclk(i915);
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intel_init_pch_refclk(display);
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}
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static void hsw_ddi_spll_disable(struct intel_display *display,
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struct intel_shared_dpll *pll)
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{
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struct drm_i915_private *i915 = to_i915(display->drm);
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enum intel_dpll_id id = pll->info->id;
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intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);
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@ -743,7 +741,7 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
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* that depend on it have been shut down.
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*/
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if (display->dpll.pch_ssc_use & BIT(id))
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intel_init_pch_refclk(i915);
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intel_init_pch_refclk(display);
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}
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static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
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@ -613,18 +613,16 @@ void lpt_pch_disable(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct intel_display *display = to_intel_display(crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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lpt_disable_pch_transcoder(display);
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lpt_disable_iclkip(dev_priv);
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lpt_disable_iclkip(display);
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}
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void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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u32 tmp;
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if ((intel_de_read(display, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
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@ -639,7 +637,7 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
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intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
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&crtc_state->fdi_m_n);
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crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
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crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(display);
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}
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void intel_pch_sanitize(struct intel_display *display)
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@ -11,27 +11,28 @@
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#include "intel_pch_refclk.h"
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#include "intel_sbi.h"
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static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
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static void lpt_fdi_reset_mphy(struct intel_display *display)
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{
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intel_de_rmw(dev_priv, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
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intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
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if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
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if (wait_for_us(intel_de_read(display, SOUTH_CHICKEN2) &
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FDI_MPHY_IOSFSB_RESET_STATUS, 100))
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drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
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drm_err(display->drm, "FDI mPHY reset assert timeout\n");
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intel_de_rmw(dev_priv, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
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intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
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if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
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if (wait_for_us((intel_de_read(display, SOUTH_CHICKEN2) &
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FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
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drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
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drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");
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}
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/* WaMPhyProgramming:hsw */
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static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
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static void lpt_fdi_program_mphy(struct intel_display *display)
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{
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struct drm_i915_private *dev_priv = to_i915(display->drm);
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u32 tmp;
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lpt_fdi_reset_mphy(dev_priv);
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lpt_fdi_reset_mphy(display);
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tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
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tmp &= ~(0xFF << 24);
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@ -103,11 +104,12 @@ static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
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intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
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}
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void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
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void lpt_disable_iclkip(struct intel_display *display)
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{
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struct drm_i915_private *dev_priv = to_i915(display->drm);
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u32 temp;
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intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
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intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_GATE);
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intel_sbi_lock(dev_priv);
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@ -175,24 +177,25 @@ int lpt_iclkip(const struct intel_crtc_state *crtc_state)
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/* Program iCLKIP clock to the desired frequency */
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void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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int clock = crtc_state->hw.adjusted_mode.crtc_clock;
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struct iclkip_params p;
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u32 temp;
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lpt_disable_iclkip(dev_priv);
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lpt_disable_iclkip(display);
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lpt_compute_iclkip(&p, clock);
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drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
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drm_WARN_ON(display->drm, lpt_iclkip_freq(&p) != clock);
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/* This should not happen with any sane values */
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drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
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drm_WARN_ON(display->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
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~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
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drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
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drm_WARN_ON(display->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
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~SBI_SSCDIVINTPHASE_INCVAL_MASK);
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drm_dbg_kms(&dev_priv->drm,
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drm_dbg_kms(display->drm,
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"iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
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clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);
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@ -224,15 +227,16 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
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/* Wait for initialization time */
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udelay(24);
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intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
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intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
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}
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int lpt_get_iclkip(struct drm_i915_private *dev_priv)
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int lpt_get_iclkip(struct intel_display *display)
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{
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struct drm_i915_private *dev_priv = to_i915(display->drm);
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struct iclkip_params p;
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u32 temp;
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if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
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if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
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return 0;
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iclkip_params_init(&p);
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@ -268,15 +272,16 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
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* - Sequence to enable CLKOUT_DP without spread
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* - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
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*/
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static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
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static void lpt_enable_clkout_dp(struct intel_display *display,
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bool with_spread, bool with_fdi)
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{
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struct drm_i915_private *dev_priv = to_i915(display->drm);
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u32 reg, tmp;
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if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
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if (drm_WARN(display->drm, with_fdi && !with_spread,
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"FDI requires downspread\n"))
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with_spread = true;
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if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
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if (drm_WARN(display->drm, HAS_PCH_LPT_LP(dev_priv) &&
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with_fdi, "LP PCH doesn't have FDI\n"))
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with_fdi = false;
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@ -295,7 +300,7 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
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intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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if (with_fdi)
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lpt_fdi_program_mphy(dev_priv);
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lpt_fdi_program_mphy(display);
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}
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reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
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@ -307,8 +312,9 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
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}
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/* Sequence to disable CLKOUT_DP */
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void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
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void lpt_disable_clkout_dp(struct intel_display *display)
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{
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struct drm_i915_private *dev_priv = to_i915(display->drm);
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u32 reg, tmp;
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intel_sbi_lock(dev_priv);
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@ -364,15 +370,16 @@ static const u16 sscdivintphase[] = {
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* < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
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* change in clock period = -(steps / 10) * 5.787 ps
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*/
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static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
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static void lpt_bend_clkout_dp(struct intel_display *display, int steps)
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{
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struct drm_i915_private *dev_priv = to_i915(display->drm);
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u32 tmp;
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int idx = BEND_IDX(steps);
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if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
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if (drm_WARN_ON(display->drm, steps % 5 != 0))
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return;
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if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
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if (drm_WARN_ON(display->drm, idx >= ARRAY_SIZE(sscdivintphase)))
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return;
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intel_sbi_lock(dev_priv);
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@ -393,10 +400,10 @@ static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
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#undef BEND_IDX
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static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
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static bool spll_uses_pch_ssc(struct intel_display *display)
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{
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u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
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u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
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u32 fuse_strap = intel_de_read(display, FUSE_STRAP);
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u32 ctl = intel_de_read(display, SPLL_CTL);
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if ((ctl & SPLL_PLL_ENABLE) == 0)
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return false;
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@ -405,18 +412,17 @@ static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
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(fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
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return true;
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if (IS_BROADWELL(dev_priv) &&
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if (display->platform.broadwell &&
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(ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
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return true;
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return false;
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}
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static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
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enum intel_dpll_id id)
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static bool wrpll_uses_pch_ssc(struct intel_display *display, enum intel_dpll_id id)
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{
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u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
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u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
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u32 fuse_strap = intel_de_read(display, FUSE_STRAP);
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u32 ctl = intel_de_read(display, WRPLL_CTL(id));
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if ((ctl & WRPLL_PLL_ENABLE) == 0)
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return false;
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@ -424,7 +430,7 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
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if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
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return true;
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if ((IS_BROADWELL(dev_priv) || IS_HASWELL_ULT(dev_priv)) &&
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if ((display->platform.broadwell || display->platform.haswell_ult) &&
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(ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
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(fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
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return true;
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@ -432,12 +438,12 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
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return false;
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}
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static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
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static void lpt_init_pch_refclk(struct intel_display *display)
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{
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struct intel_encoder *encoder;
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bool has_fdi = false;
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for_each_intel_encoder(&dev_priv->drm, encoder) {
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for_each_intel_encoder(display->drm, encoder) {
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switch (encoder->type) {
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case INTEL_OUTPUT_ANALOG:
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has_fdi = true;
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@ -462,37 +468,37 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
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* clock hierarchy. That would also allow us to do
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* clock bending finally.
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*/
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dev_priv->display.dpll.pch_ssc_use = 0;
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display->dpll.pch_ssc_use = 0;
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if (spll_uses_pch_ssc(dev_priv)) {
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drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
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dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);
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if (spll_uses_pch_ssc(display)) {
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drm_dbg_kms(display->drm, "SPLL using PCH SSC\n");
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display->dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);
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}
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if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
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drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
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dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
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if (wrpll_uses_pch_ssc(display, DPLL_ID_WRPLL1)) {
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drm_dbg_kms(display->drm, "WRPLL1 using PCH SSC\n");
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display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
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}
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if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
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drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
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dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
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if (wrpll_uses_pch_ssc(display, DPLL_ID_WRPLL2)) {
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drm_dbg_kms(display->drm, "WRPLL2 using PCH SSC\n");
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display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
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||||
}
|
||||
|
||||
if (dev_priv->display.dpll.pch_ssc_use)
|
||||
if (display->dpll.pch_ssc_use)
|
||||
return;
|
||||
|
||||
if (has_fdi) {
|
||||
lpt_bend_clkout_dp(dev_priv, 0);
|
||||
lpt_enable_clkout_dp(dev_priv, true, true);
|
||||
lpt_bend_clkout_dp(display, 0);
|
||||
lpt_enable_clkout_dp(display, true, true);
|
||||
} else {
|
||||
lpt_disable_clkout_dp(dev_priv);
|
||||
lpt_disable_clkout_dp(display);
|
||||
}
|
||||
}
|
||||
|
||||
static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
|
||||
static void ilk_init_pch_refclk(struct intel_display *display)
|
||||
{
|
||||
struct intel_display *display = &dev_priv->display;
|
||||
struct drm_i915_private *dev_priv = to_i915(display->drm);
|
||||
struct intel_encoder *encoder;
|
||||
struct intel_shared_dpll *pll;
|
||||
int i;
|
||||
|
|
@ -607,7 +613,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
|
|||
|
||||
/* SSC must be turned on before enabling the CPU output */
|
||||
if (intel_panel_use_ssc(display) && can_ssc) {
|
||||
drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
|
||||
drm_dbg_kms(display->drm, "Using SSC on panel\n");
|
||||
val |= DREF_SSC1_ENABLE;
|
||||
} else {
|
||||
val &= ~DREF_SSC1_ENABLE;
|
||||
|
|
@ -623,7 +629,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
|
|||
/* Enable CPU source on CPU attached eDP */
|
||||
if (has_cpu_edp) {
|
||||
if (intel_panel_use_ssc(display) && can_ssc) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
drm_dbg_kms(display->drm,
|
||||
"Using SSC on eDP\n");
|
||||
val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
|
||||
} else {
|
||||
|
|
@ -670,10 +676,12 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
|
|||
/*
|
||||
* Initialize reference clocks when the driver loads
|
||||
*/
|
||||
void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
|
||||
void intel_init_pch_refclk(struct intel_display *display)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(display->drm);
|
||||
|
||||
if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
|
||||
ilk_init_pch_refclk(dev_priv);
|
||||
ilk_init_pch_refclk(display);
|
||||
else if (HAS_PCH_LPT(dev_priv))
|
||||
lpt_init_pch_refclk(dev_priv);
|
||||
lpt_init_pch_refclk(display);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,25 +8,25 @@
|
|||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct drm_i915_private;
|
||||
struct intel_crtc_state;
|
||||
struct intel_display;
|
||||
|
||||
#ifdef I915
|
||||
void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);
|
||||
void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
|
||||
int lpt_get_iclkip(struct drm_i915_private *dev_priv);
|
||||
void lpt_disable_iclkip(struct intel_display *display);
|
||||
int lpt_get_iclkip(struct intel_display *display);
|
||||
int lpt_iclkip(const struct intel_crtc_state *crtc_state);
|
||||
|
||||
void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
|
||||
void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
|
||||
void intel_init_pch_refclk(struct intel_display *display);
|
||||
void lpt_disable_clkout_dp(struct intel_display *display);
|
||||
#else
|
||||
static inline void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
}
|
||||
static inline void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
|
||||
static inline void lpt_disable_iclkip(struct intel_display *display)
|
||||
{
|
||||
}
|
||||
static inline int lpt_get_iclkip(struct drm_i915_private *dev_priv)
|
||||
static inline int lpt_get_iclkip(struct intel_display *display)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -34,10 +34,10 @@ static inline int lpt_iclkip(const struct intel_crtc_state *crtc_state)
|
|||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
|
||||
static inline void intel_init_pch_refclk(struct intel_display *display)
|
||||
{
|
||||
}
|
||||
static inline void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
|
||||
static inline void lpt_disable_clkout_dp(struct intel_display *display)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1211,7 +1211,7 @@ static int i915_drm_resume(struct drm_device *dev)
|
|||
|
||||
intel_pps_unlock_regs_wa(display);
|
||||
|
||||
intel_init_pch_refclk(dev_priv);
|
||||
intel_init_pch_refclk(display);
|
||||
|
||||
/*
|
||||
* Interrupts have to be enabled before any batches are run. If not the
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue