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Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue
Tony Nguyen says: ==================== Intel Wired LAN Driver Updates 2025-04-02 (igc, e1000e, ixgbe, idpf) For igc: Joe Damato removes unmapping of XSK queues from NAPI instance. Zdenek Bouska swaps condition checks/call to prevent AF_XDP Tx drops with low budget value. For e1000e: Vitaly adjusts Kumeran interface configuration to prevent MDI errors. For ixgbe: Piotr clears PHY high values on media type detection to ensure stale values are not used. For idpf: Emil adjusts shutdown calls to prevent NULL pointer dereference. * '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue: idpf: fix adapter NULL pointer dereference on reboot ixgbe: fix media type detection for E610 device e1000e: change k1 configuration on MTP and later platforms igc: Fix TX drops in XDP ZC igc: Fix XSK queue NAPI ID mapping ==================== Link: https://patch.msgid.link/20250402173900.1957261-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
commit
915873752c
8 changed files with 93 additions and 14 deletions
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@ -803,4 +803,7 @@
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/* SerDes Control */
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#define E1000_GEN_POLL_TIMEOUT 640
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#define E1000_FEXTNVM12_PHYPD_CTRL_MASK 0x00C00000
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#define E1000_FEXTNVM12_PHYPD_CTRL_P1 0x00800000
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#endif /* _E1000_DEFINES_H_ */
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@ -285,6 +285,45 @@ static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
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}
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}
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/**
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* e1000_reconfigure_k1_exit_timeout - reconfigure K1 exit timeout to
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* align to MTP and later platform requirements.
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* @hw: pointer to the HW structure
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*
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* Context: PHY semaphore must be held by caller.
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* Return: 0 on success, negative on failure
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*/
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static s32 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw)
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{
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u16 phy_timeout;
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u32 fextnvm12;
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s32 ret_val;
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if (hw->mac.type < e1000_pch_mtp)
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return 0;
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/* Change Kumeran K1 power down state from P0s to P1 */
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fextnvm12 = er32(FEXTNVM12);
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fextnvm12 &= ~E1000_FEXTNVM12_PHYPD_CTRL_MASK;
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fextnvm12 |= E1000_FEXTNVM12_PHYPD_CTRL_P1;
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ew32(FEXTNVM12, fextnvm12);
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/* Wait for the interface the settle */
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usleep_range(1000, 1100);
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/* Change K1 exit timeout */
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ret_val = e1e_rphy_locked(hw, I217_PHY_TIMEOUTS_REG,
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&phy_timeout);
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if (ret_val)
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return ret_val;
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phy_timeout &= ~I217_PHY_TIMEOUTS_K1_EXIT_TO_MASK;
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phy_timeout |= 0xF00;
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return e1e_wphy_locked(hw, I217_PHY_TIMEOUTS_REG,
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phy_timeout);
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}
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/**
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* e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
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* @hw: pointer to the HW structure
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@ -327,15 +366,22 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
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* LANPHYPC Value bit to force the interconnect to PCIe mode.
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*/
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switch (hw->mac.type) {
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case e1000_pch_mtp:
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case e1000_pch_lnp:
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case e1000_pch_ptp:
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case e1000_pch_nvp:
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/* At this point the PHY might be inaccessible so don't
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* propagate the failure
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*/
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if (e1000_reconfigure_k1_exit_timeout(hw))
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e_dbg("Failed to reconfigure K1 exit timeout\n");
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fallthrough;
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case e1000_pch_lpt:
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case e1000_pch_spt:
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case e1000_pch_cnp:
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_lnp:
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case e1000_pch_ptp:
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case e1000_pch_nvp:
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if (e1000_phy_is_accessible_pchlan(hw))
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break;
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@ -419,8 +465,20 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
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* the PHY is in.
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*/
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ret_val = hw->phy.ops.check_reset_block(hw);
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if (ret_val)
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if (ret_val) {
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e_err("ME blocked access to PHY after reset\n");
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goto out;
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}
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if (hw->mac.type >= e1000_pch_mtp) {
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val) {
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e_err("Failed to reconfigure K1 exit timeout\n");
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goto out;
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}
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ret_val = e1000_reconfigure_k1_exit_timeout(hw);
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hw->phy.ops.release(hw);
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}
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}
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out:
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@ -4888,6 +4946,18 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
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u16 i;
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e1000_initialize_hw_bits_ich8lan(hw);
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if (hw->mac.type >= e1000_pch_mtp) {
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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ret_val = e1000_reconfigure_k1_exit_timeout(hw);
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hw->phy.ops.release(hw);
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if (ret_val) {
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e_dbg("Error failed to reconfigure K1 exit timeout\n");
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return ret_val;
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}
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}
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/* Initialize identification LED */
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ret_val = mac->ops.id_led_init(hw);
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@ -219,6 +219,10 @@
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#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)
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#define I217_PLL_CLOCK_GATE_MASK 0x07FF
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/* PHY Timeouts */
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#define I217_PHY_TIMEOUTS_REG PHY_REG(770, 21)
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#define I217_PHY_TIMEOUTS_K1_EXIT_TO_MASK 0x0FC0
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#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
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/* Inband Control */
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@ -87,7 +87,11 @@ destroy_wqs:
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*/
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static void idpf_shutdown(struct pci_dev *pdev)
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{
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idpf_remove(pdev);
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struct idpf_adapter *adapter = pci_get_drvdata(pdev);
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cancel_delayed_work_sync(&adapter->vc_event_task);
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idpf_vc_core_deinit(adapter);
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idpf_deinit_dflt_mbx(adapter);
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if (system_state == SYSTEM_POWER_OFF)
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pci_set_power_state(pdev, PCI_D3hot);
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@ -337,8 +337,6 @@ struct igc_adapter {
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struct igc_led_classdev *leds;
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};
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void igc_set_queue_napi(struct igc_adapter *adapter, int q_idx,
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struct napi_struct *napi);
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void igc_up(struct igc_adapter *adapter);
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void igc_down(struct igc_adapter *adapter);
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int igc_open(struct net_device *netdev);
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@ -3042,7 +3042,7 @@ static void igc_xdp_xmit_zc(struct igc_ring *ring)
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* descriptors. Therefore, to be safe, we always ensure we have at least
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* 4 descriptors available.
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*/
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while (xsk_tx_peek_desc(pool, &xdp_desc) && budget >= 4) {
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while (budget >= 4 && xsk_tx_peek_desc(pool, &xdp_desc)) {
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struct igc_metadata_request meta_req;
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struct xsk_tx_metadata *meta = NULL;
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struct igc_tx_buffer *bi;
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@ -5022,8 +5022,8 @@ static int igc_sw_init(struct igc_adapter *adapter)
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return 0;
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}
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void igc_set_queue_napi(struct igc_adapter *adapter, int vector,
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struct napi_struct *napi)
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static void igc_set_queue_napi(struct igc_adapter *adapter, int vector,
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struct napi_struct *napi)
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{
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struct igc_q_vector *q_vector = adapter->q_vector[vector];
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@ -97,7 +97,6 @@ static int igc_xdp_enable_pool(struct igc_adapter *adapter,
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napi_disable(napi);
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}
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igc_set_queue_napi(adapter, queue_id, NULL);
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set_bit(IGC_RING_FLAG_AF_XDP_ZC, &rx_ring->flags);
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set_bit(IGC_RING_FLAG_AF_XDP_ZC, &tx_ring->flags);
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@ -147,7 +146,6 @@ static int igc_xdp_disable_pool(struct igc_adapter *adapter, u16 queue_id)
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xsk_pool_dma_unmap(pool, IGC_RX_DMA_ATTR);
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clear_bit(IGC_RING_FLAG_AF_XDP_ZC, &rx_ring->flags);
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clear_bit(IGC_RING_FLAG_AF_XDP_ZC, &tx_ring->flags);
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igc_set_queue_napi(adapter, queue_id, napi);
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if (needs_reset) {
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napi_enable(napi);
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@ -1453,9 +1453,11 @@ enum ixgbe_media_type ixgbe_get_media_type_e610(struct ixgbe_hw *hw)
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hw->link.link_info.phy_type_low = 0;
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} else {
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highest_bit = fls64(le64_to_cpu(pcaps.phy_type_low));
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if (highest_bit)
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if (highest_bit) {
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hw->link.link_info.phy_type_low =
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BIT_ULL(highest_bit - 1);
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hw->link.link_info.phy_type_high = 0;
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}
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}
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}
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