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misc: pci_endpoint_test: Add BAR subrange mapping test case
Add a new PCITEST_BAR_SUBRANGE ioctl to exercise EPC BAR subrange
mapping end-to-end.
The test programs a simple 2-subrange layout on the endpoint (via
pci-epf-test) and verifies that:
- the endpoint-provided per-subrange signature bytes are observed at
the expected PCIe BAR offsets, and
- writes to each subrange are routed to the correct backing region
(i.e. the submap order is applied rather than accidentally working
due to an identity mapping).
Return -EOPNOTSUPP when the endpoint does not advertise subrange
mapping, -ENODATA when the BAR is disabled, and -EBUSY when the BAR is
reserved for the test register space.
Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260124145012.2794108-8-den@valinux.co.jp
This commit is contained in:
Koichiro Den
Bjorn Helgaas
parent
6c5e610142
commit
8cf82bb558
2 changed files with 203 additions and 1 deletions
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@ -39,6 +39,8 @@
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#define COMMAND_COPY BIT(5)
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#define COMMAND_ENABLE_DOORBELL BIT(6)
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#define COMMAND_DISABLE_DOORBELL BIT(7)
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#define COMMAND_BAR_SUBRANGE_SETUP BIT(8)
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#define COMMAND_BAR_SUBRANGE_CLEAR BIT(9)
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#define PCI_ENDPOINT_TEST_STATUS 0x8
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#define STATUS_READ_SUCCESS BIT(0)
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@ -55,6 +57,10 @@
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#define STATUS_DOORBELL_ENABLE_FAIL BIT(11)
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#define STATUS_DOORBELL_DISABLE_SUCCESS BIT(12)
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#define STATUS_DOORBELL_DISABLE_FAIL BIT(13)
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#define STATUS_BAR_SUBRANGE_SETUP_SUCCESS BIT(14)
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#define STATUS_BAR_SUBRANGE_SETUP_FAIL BIT(15)
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#define STATUS_BAR_SUBRANGE_CLEAR_SUCCESS BIT(16)
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#define STATUS_BAR_SUBRANGE_CLEAR_FAIL BIT(17)
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#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
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#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
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@ -77,6 +83,7 @@
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#define CAP_MSI BIT(1)
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#define CAP_MSIX BIT(2)
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#define CAP_INTX BIT(3)
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#define CAP_SUBRANGE_MAPPING BIT(4)
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#define PCI_ENDPOINT_TEST_DB_BAR 0x34
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#define PCI_ENDPOINT_TEST_DB_OFFSET 0x38
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@ -100,6 +107,8 @@
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#define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588
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#define PCI_ENDPOINT_TEST_BAR_SUBRANGE_NSUB 2
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static DEFINE_IDA(pci_endpoint_test_ida);
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#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
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@ -414,6 +423,193 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
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return 0;
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}
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static u8 pci_endpoint_test_subrange_sig_byte(enum pci_barno barno,
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unsigned int subno)
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{
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return 0x50 + (barno * 8) + subno;
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}
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static u8 pci_endpoint_test_subrange_test_byte(enum pci_barno barno,
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unsigned int subno)
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{
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return 0xa0 + (barno * 8) + subno;
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}
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static int pci_endpoint_test_bar_subrange_cmd(struct pci_endpoint_test *test,
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enum pci_barno barno, u32 command,
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u32 ok_bit, u32 fail_bit)
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{
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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int irq_type = test->irq_type;
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u32 status;
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if (irq_type < PCITEST_IRQ_TYPE_INTX ||
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irq_type > PCITEST_IRQ_TYPE_MSIX) {
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dev_err(dev, "Invalid IRQ type\n");
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return -EINVAL;
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}
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reinit_completion(&test->irq_raised);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS, 0);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
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/* Reuse SIZE as a command parameter: bar number. */
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, barno);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, command);
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if (!wait_for_completion_timeout(&test->irq_raised,
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msecs_to_jiffies(1000)))
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return -ETIMEDOUT;
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status = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
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if (status & fail_bit)
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return -EIO;
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if (!(status & ok_bit))
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return -EIO;
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return 0;
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}
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static int pci_endpoint_test_bar_subrange_setup(struct pci_endpoint_test *test,
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enum pci_barno barno)
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{
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return pci_endpoint_test_bar_subrange_cmd(test, barno,
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COMMAND_BAR_SUBRANGE_SETUP,
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STATUS_BAR_SUBRANGE_SETUP_SUCCESS,
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STATUS_BAR_SUBRANGE_SETUP_FAIL);
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}
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static int pci_endpoint_test_bar_subrange_clear(struct pci_endpoint_test *test,
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enum pci_barno barno)
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{
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return pci_endpoint_test_bar_subrange_cmd(test, barno,
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COMMAND_BAR_SUBRANGE_CLEAR,
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STATUS_BAR_SUBRANGE_CLEAR_SUCCESS,
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STATUS_BAR_SUBRANGE_CLEAR_FAIL);
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}
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static int pci_endpoint_test_bar_subrange(struct pci_endpoint_test *test,
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enum pci_barno barno)
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{
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u32 nsub = PCI_ENDPOINT_TEST_BAR_SUBRANGE_NSUB;
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struct device *dev = &test->pdev->dev;
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size_t sub_size, buf_size;
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resource_size_t bar_size;
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void __iomem *bar_addr;
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void *read_buf = NULL;
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int ret, clear_ret;
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size_t off, chunk;
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u32 i, exp, val;
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u8 pattern;
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if (!(test->ep_caps & CAP_SUBRANGE_MAPPING))
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return -EOPNOTSUPP;
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/*
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* The test register BAR is not safe to reprogram and write/read
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* over its full size. BAR_TEST already special-cases it to a tiny
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* range. For subrange mapping tests, let's simply skip it.
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*/
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if (barno == test->test_reg_bar)
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return -EBUSY;
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bar_size = pci_resource_len(test->pdev, barno);
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if (!bar_size)
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return -ENODATA;
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bar_addr = test->bar[barno];
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if (!bar_addr)
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return -ENOMEM;
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ret = pci_endpoint_test_bar_subrange_setup(test, barno);
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if (ret)
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return ret;
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if (bar_size % nsub || bar_size / nsub > SIZE_MAX) {
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ret = -EINVAL;
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goto out_clear;
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}
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sub_size = bar_size / nsub;
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if (sub_size < sizeof(u32)) {
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ret = -ENOSPC;
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goto out_clear;
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}
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/* Limit the temporary buffer size */
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buf_size = min_t(size_t, sub_size, SZ_1M);
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read_buf = kmalloc(buf_size, GFP_KERNEL);
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if (!read_buf) {
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ret = -ENOMEM;
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goto out_clear;
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}
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/*
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* Step 1: verify EP-provided signature per subrange. This detects
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* whether the EP actually applied the submap order.
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*/
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for (i = 0; i < nsub; i++) {
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exp = (u32)pci_endpoint_test_subrange_sig_byte(barno, i) *
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0x01010101U;
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val = ioread32(bar_addr + (i * sub_size));
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if (val != exp) {
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dev_err(dev,
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"BAR%d subrange%u signature mismatch @%#zx: exp %#08x got %#08x\n",
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barno, i, (size_t)i * sub_size, exp, val);
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ret = -EIO;
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goto out_clear;
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}
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val = ioread32(bar_addr + (i * sub_size) + sub_size - sizeof(u32));
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if (val != exp) {
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dev_err(dev,
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"BAR%d subrange%u signature mismatch @%#zx: exp %#08x got %#08x\n",
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barno, i,
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((size_t)i * sub_size) + sub_size - sizeof(u32),
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exp, val);
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ret = -EIO;
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goto out_clear;
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}
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}
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/* Step 2: write unique pattern per subrange (write all first). */
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for (i = 0; i < nsub; i++) {
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pattern = pci_endpoint_test_subrange_test_byte(barno, i);
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memset_io(bar_addr + (i * sub_size), pattern, sub_size);
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}
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/* Step 3: read back and verify (read all after all writes). */
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for (i = 0; i < nsub; i++) {
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pattern = pci_endpoint_test_subrange_test_byte(barno, i);
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for (off = 0; off < sub_size; off += chunk) {
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void *bad;
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chunk = min_t(size_t, buf_size, sub_size - off);
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memcpy_fromio(read_buf, bar_addr + (i * sub_size) + off,
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chunk);
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bad = memchr_inv(read_buf, pattern, chunk);
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if (bad) {
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size_t bad_off = (u8 *)bad - (u8 *)read_buf;
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dev_err(dev,
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"BAR%d subrange%u data mismatch @%#zx (pattern %#02x)\n",
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barno, i, (size_t)i * sub_size + off + bad_off,
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pattern);
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ret = -EIO;
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goto out_clear;
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}
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}
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}
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out_clear:
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kfree(read_buf);
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clear_ret = pci_endpoint_test_bar_subrange_clear(test, barno);
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return ret ?: clear_ret;
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}
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static int pci_endpoint_test_intx_irq(struct pci_endpoint_test *test)
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{
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u32 val;
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@ -936,12 +1132,17 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
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switch (cmd) {
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case PCITEST_BAR:
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case PCITEST_BAR_SUBRANGE:
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bar = arg;
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if (bar <= NO_BAR || bar > BAR_5)
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goto ret;
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if (is_am654_pci_dev(pdev) && bar == BAR_0)
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goto ret;
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ret = pci_endpoint_test_bar(test, bar);
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if (cmd == PCITEST_BAR)
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ret = pci_endpoint_test_bar(test, bar);
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else
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ret = pci_endpoint_test_bar_subrange(test, bar);
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break;
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case PCITEST_BARS:
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ret = pci_endpoint_test_bars(test);
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@ -22,6 +22,7 @@
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#define PCITEST_GET_IRQTYPE _IO('P', 0x9)
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#define PCITEST_BARS _IO('P', 0xa)
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#define PCITEST_DOORBELL _IO('P', 0xb)
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#define PCITEST_BAR_SUBRANGE _IO('P', 0xc)
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#define PCITEST_CLEAR_IRQ _IO('P', 0x10)
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#define PCITEST_IRQ_TYPE_UNDEFINED -1
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