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clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct
MT8196 uses a HW voter for gate enable/disable control, with set/clr/sta registers located in a separate regmap. Refactor mtk_clk_register_gate() to take a struct mtk_gate, and add a pointer to it in struct mtk_clk_gate. This allows reuse of the static gate data (including HW voter register offsets) without adding extra function arguments, and removes redundant duplication in the runtime data struct. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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1 changed files with 19 additions and 33 deletions
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@ -17,10 +17,7 @@
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struct mtk_clk_gate {
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struct clk_hw hw;
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struct regmap *regmap;
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int set_ofs;
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int clr_ofs;
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int sta_ofs;
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u8 bit;
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const struct mtk_gate *gate;
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};
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static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
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@ -33,9 +30,9 @@ static u32 mtk_get_clockgating(struct clk_hw *hw)
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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u32 val;
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regmap_read(cg->regmap, cg->sta_ofs, &val);
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regmap_read(cg->regmap, cg->gate->regs->sta_ofs, &val);
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return val & BIT(cg->bit);
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return val & BIT(cg->gate->shift);
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}
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static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
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@ -52,28 +49,30 @@ static void mtk_cg_set_bit(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
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regmap_write(cg->regmap, cg->gate->regs->set_ofs, BIT(cg->gate->shift));
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}
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static void mtk_cg_clr_bit(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
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regmap_write(cg->regmap, cg->gate->regs->clr_ofs, BIT(cg->gate->shift));
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}
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static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
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regmap_set_bits(cg->regmap, cg->gate->regs->sta_ofs,
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BIT(cg->gate->shift));
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}
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static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
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regmap_clear_bits(cg->regmap, cg->gate->regs->sta_ofs,
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BIT(cg->gate->shift));
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}
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static int mtk_cg_enable(struct clk_hw *hw)
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@ -152,12 +151,9 @@ const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
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};
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EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
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static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
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const char *parent_name,
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struct regmap *regmap, int set_ofs,
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int clr_ofs, int sta_ofs, u8 bit,
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const struct clk_ops *ops,
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unsigned long flags)
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static struct clk_hw *mtk_clk_register_gate(struct device *dev,
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const struct mtk_gate *gate,
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struct regmap *regmap)
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{
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struct mtk_clk_gate *cg;
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int ret;
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@ -167,18 +163,14 @@ static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name
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if (!cg)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags | CLK_SET_RATE_PARENT;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.ops = ops;
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init.name = gate->name;
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init.flags = gate->flags | CLK_SET_RATE_PARENT;
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init.parent_names = gate->parent_name ? &gate->parent_name : NULL;
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init.num_parents = gate->parent_name ? 1 : 0;
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init.ops = gate->ops;
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cg->regmap = regmap;
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cg->set_ofs = set_ofs;
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cg->clr_ofs = clr_ofs;
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cg->sta_ofs = sta_ofs;
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cg->bit = bit;
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cg->gate = gate;
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cg->hw.init = &init;
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ret = clk_hw_register(dev, &cg->hw);
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@ -228,13 +220,7 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
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continue;
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}
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hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
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regmap,
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gate->regs->set_ofs,
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gate->regs->clr_ofs,
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gate->regs->sta_ofs,
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gate->shift, gate->ops,
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gate->flags);
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hw = mtk_clk_register_gate(dev, gate, regmap);
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if (IS_ERR(hw)) {
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pr_err("Failed to register clk %s: %pe\n", gate->name,
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