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accel/ivpu: Enable MCA ECC signalling based on MSR

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Add new boot parameter for NPU5+ that enables
ECC signalling for on-chip memory based on the value
of MSR_INTEGRITY_CAPS register.

Signed-off-by: Tomasz Rusinowicz <tomasz.rusinowicz@intel.com>
Signed-off-by: Maciej Falkowski <maciej.falkowski@linux.intel.com>
Reviewed-by: Karol Wachowski <karol.wachowski@linux.intel.com>
Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com>
Link: https://lore.kernel.org/r/20250925145020.1446208-1-maciej.falkowski@linux.intel.com
This commit is contained in:
Tomasz Rusinowicz 2025-09-25 16:50:20 +02:00 • committed by Karol Wachowski
parent 306e6407ed
commit 87a23fe296
3 changed files with 28 additions and 0 deletions
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4
drivers/accel/ivpu/ivpu_fw.c
View file

@ -606,6 +606,8 @@ static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_
boot_params->system_time_us);
ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = 0x%x\n",
boot_params->power_profile);
ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_uses_ecc_mca_signal = 0x%x\n",
boot_params->vpu_uses_ecc_mca_signal);
}
void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
@ -708,6 +710,8 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
boot_params->d0i3_entry_vpu_ts = 0;
if (IVPU_WA(disable_d0i2))
boot_params->power_profile |= BIT(1);
boot_params->vpu_uses_ecc_mca_signal =
ivpu_hw_uses_ecc_mca_signal(vdev) ? VPU_BOOT_MCA_ECC_BOTH : 0;
boot_params->system_time_us = ktime_to_us(ktime_get_real());
wmb(); /* Flush WC buffers after writing bootparams */

23
drivers/accel/ivpu/ivpu_hw.c
View file

@ -8,6 +8,8 @@
#include "ivpu_hw_btrs.h"
#include "ivpu_hw_ip.h"
#include <asm/msr-index.h>
#include <asm/msr.h>
#include <linux/dmi.h>
#include <linux/fault-inject.h>
#include <linux/pm_runtime.h>
@ -22,6 +24,8 @@ MODULE_PARM_DESC(fail_hw, "<interval>,<probability>,<space>,<times>");
#define FW_SHARED_MEM_ALIGNMENT SZ_512K /* VPU MTRR limitation */
#define ECC_MCA_SIGNAL_ENABLE_MASK 0xff
static char *platform_to_str(u32 platform)
{
switch (platform) {
@ -395,3 +399,22 @@ irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr)
pm_runtime_mark_last_busy(vdev->drm.dev);
return IRQ_HANDLED;
}
bool ivpu_hw_uses_ecc_mca_signal(struct ivpu_device *vdev)
{
unsigned long long msr_integrity_caps;
int ret;
if (ivpu_hw_ip_gen(vdev) < IVPU_HW_IP_50XX)
return false;
ret = rdmsrq_safe(MSR_INTEGRITY_CAPS, &msr_integrity_caps);
if (ret) {
ivpu_warn(vdev, "Error reading MSR_INTEGRITY_CAPS: %d", ret);
return false;
}
ivpu_dbg(vdev, MISC, "MSR_INTEGRITY_CAPS: 0x%llx\n", msr_integrity_caps);
return msr_integrity_caps & ECC_MCA_SIGNAL_ENABLE_MASK;
}

1
drivers/accel/ivpu/ivpu_hw.h
View file

@ -63,6 +63,7 @@ void ivpu_irq_handlers_init(struct ivpu_device *vdev);
void ivpu_hw_irq_enable(struct ivpu_device *vdev);
void ivpu_hw_irq_disable(struct ivpu_device *vdev);
irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr);
bool ivpu_hw_uses_ecc_mca_signal(struct ivpu_device *vdev);
static inline u32 ivpu_hw_btrs_irq_handler(struct ivpu_device *vdev, int irq)
{