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dt-bindings: phy: google: Add Google Tensor G5 USB PHY
Document the device tree bindings for the USB PHY interfaces integrated with the DWC3 controller on Google Tensor SoCs, starting with G5 generation (Laguna). The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Due to a complete architectural overhaul in the Google Tensor G5, the existing Samsung/Exynos USB PHY binding for older generations of Google silicons such as gs101 are no longer compatible, necessitating this new device tree binding. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Roy Luo <royluo@google.com> Link: https://patch.msgid.link/20251227-phyb4-v10-1-e8caf6b93fe7@google.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Roy Luo
Vinod Koul
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Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
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Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2025, Google LLC
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/google,lga-usb-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Google Tensor Series G5 (Laguna) USB PHY
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maintainers:
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- Roy Luo <royluo@google.com>
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description:
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Describes the USB PHY interfaces integrated with the DWC3 USB controller on
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Google Tensor SoCs, starting with the G5 generation (laguna).
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Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP
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and USB3.2/DisplayPort combo PHY IP.
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properties:
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compatible:
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const: google,lga-usb-phy
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reg:
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items:
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- description: USB3.2/DisplayPort combo PHY core registers.
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- description: USB3.2/DisplayPort combo PHY Type-C Assist registers.
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- description: eUSB 2.0 PHY core registers.
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- description: Top-level wrapper registers for the integrated PHYs.
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reg-names:
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items:
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- const: usb3_core
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- const: usb3_tca
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- const: usb2_core
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- const: usbdp_top
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"#phy-cells":
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description: |
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The phandle's argument in the PHY specifier selects one of the three
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following PHY interfaces.
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- 0 for USB high-speed.
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- 1 for USB super-speed.
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- 2 for DisplayPort.
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const: 1
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clocks:
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items:
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- description: USB2 PHY clock.
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- description: USB2 PHY APB clock.
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- description: USB3.2/DisplayPort combo PHY clock.
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- description: USB3.2/DisplayPort combo PHY firmware clock.
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clock-names:
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items:
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- const: usb2
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- const: usb2_apb
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- const: usb3
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- const: usb3_fw
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resets:
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items:
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- description: USB2 PHY reset.
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- description: USB2 PHY APB reset.
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- description: USB3.2/DisplayPort combo PHY reset.
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reset-names:
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items:
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- const: usb2
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- const: usb2_apb
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- const: usb3
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power-domains:
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maxItems: 1
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orientation-switch:
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type: boolean
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description:
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Indicates the PHY as a handler of USB Type-C orientation changes
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google,usb-cfg-csr:
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description:
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A phandle to a syscon node used to access the USB configuration
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registers. These registers are the top-level wrapper of the USB
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subsystem and provide control and status for the integrated USB
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controller and USB PHY.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to the syscon node.
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- description: USB2 PHY configuration register offset.
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required:
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- compatible
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- reg
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- reg-names
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- "#phy-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- orientation-switch
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- google,usb-cfg-csr
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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usb-phy@c410000 {
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compatible = "google,lga-usb-phy";
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reg = <0 0x0c410000 0 0x20000>,
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<0 0x0c430000 0 0x1000>,
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<0 0x0c440000 0 0x10000>,
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<0 0x0c637000 0 0xa0>;
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reg-names = "usb3_core", "usb3_tca", "usb2_core", "usbdp_top";
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#phy-cells = <1>;
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clocks = <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>,
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<&hsion_usb3_phy_clk>, <&hsion_usb3_phy_fw_clk>;
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clock-names = "usb2", "usb2_apb", "usb3", "usb3_fw";
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resets = <&hsion_resets_usb2_phy>,
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<&hsion_resets_u2phy_apb>,
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<&hsion_resets_usb3_phy>;
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reset-names = "usb2", "usb2_apb", "usb3";
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power-domains = <&hsio_n_usb_pd>;
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orientation-switch;
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google,usb-cfg-csr = <&usb_cfg_csr 0x14>;
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};
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};
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...
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@ -10723,6 +10723,7 @@ S: Maintained
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P: Documentation/process/maintainer-soc-clean-dts.rst
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C: irc://irc.oftc.net/pixel6-kernel-dev
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F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
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F: Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml
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F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml
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F: arch/arm64/boot/dts/exynos/google/
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F: drivers/clk/samsung/clk-gs101.c
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