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x86/mce: Add support for physical address valid bit

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Starting with Zen6, AMD's Scalable MCA systems will incorporate two new bits in
MCA_STATUS and MCA_CONFIG MSRs. These bits will indicate if a valid System
Physical Address (SPA) is present in MCA_ADDR.

PhysAddrValidSupported bit (MCA_CONFIG[11]) serves as the architectural
indicator and states if PhysAddrV bit (MCA_STATUS[54]) is Reserved or if it
indicates validity of SPA in MCA_ADDR.

PhysAddrV bit (MCA_STATUS[54]) advertises if MCA_ADDR contains valid SPA or if
it is implementation specific.

Use and prefer MCA_STATUS[PhysAddrV] when checking for a usable address.

Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/20251118191731.181269-1-avadhut.naik@amd.com
This commit is contained in:
Avadhut Naik 2025-11-18 19:15:03 +00:00 • committed by Borislav Petkov (AMD)
parent eeb3f76d73
commit 821f5fe4db
2 changed files with 15 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

2
arch/x86/include/asm/mce.h
View file

@ -48,6 +48,7 @@
/* AMD-specific bits */
#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
#define MCI_STATUS_PADDRV BIT_ULL(54) /* Valid System Physical Address */
#define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */
#define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */
#define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */
@ -62,6 +63,7 @@
*/
#define MCI_CONFIG_MCAX 0x1
#define MCI_CONFIG_FRUTEXT BIT_ULL(9)
#define MCI_CONFIG_PADDRV BIT_ULL(11)
#define MCI_IPID_MCATYPE 0xFFFF0000
#define MCI_IPID_HWID 0xFFF

16
arch/x86/kernel/cpu/mce/amd.c
View file

@ -87,6 +87,8 @@ struct smca_bank {
const struct smca_hwid *hwid;
u32 id; /* Value of MCA_IPID[InstanceId]. */
u8 sysfs_id; /* Value used for sysfs name. */
u64 paddrv :1, /* Physical Address Valid bit in MCA_CONFIG */
__reserved :63;
};
static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
@ -327,6 +329,9 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
if (low & MCI_CONFIG_PADDRV)
this_cpu_ptr(smca_banks)[bank].paddrv = 1;
wrmsr(smca_config, low, high);
}
@ -790,9 +795,9 @@ bool amd_mce_is_memory_error(struct mce *m)
}
/*
* AMD systems do not have an explicit indicator that the value in MCA_ADDR is
* a system physical address. Therefore, individual cases need to be detected.
* Future cases and checks will be added as needed.
* Some AMD systems have an explicit indicator that the value in MCA_ADDR is a
* system physical address. Individual cases though, need to be detected for
* other systems. Future cases will be added as needed.
*
* 1) General case
* a) Assume address is not usable.
@ -806,6 +811,8 @@ bool amd_mce_is_memory_error(struct mce *m)
* a) Reported in legacy bank 4 with extended error code (XEC) 8.
* b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore,
* this bit should not be checked.
* 4) MCI_STATUS_PADDRVAL is set
* a) Will provide a valid system physical address.
*
* NOTE: SMCA UMC memory errors fall into case #1.
*/
@ -819,6 +826,9 @@ bool amd_mce_usable_address(struct mce *m)
return false;
}
if (this_cpu_ptr(smca_banks)[m->bank].paddrv)
return m->status & MCI_STATUS_PADDRV;
/* Check poison bit for all other bank types. */
if (m->status & MCI_STATUS_POISON)
return true;