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spmi: spmi-pmic-arb: add support for PMIC arbiter v8
PMIC arbiter v8 supports up to 4 SPMI buses and up to 8192 PMIC peripherals. Its register map differs from v7 as several fields increased in size. Add support for PMIC arbiter version 8. Signed-off-by: David Collins <david.collins@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://patch.msgid.link/20260123182039.224314-10-sboyd@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
David Collins
Greg Kroah-Hartman
parent
0914498171
commit
815be38ad8
1 changed files with 256 additions and 50 deletions
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@ -2,6 +2,8 @@
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/*
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* Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitmap.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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@ -25,12 +27,12 @@
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#define PMIC_ARB_VERSION_V3_MIN 0x30000000
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#define PMIC_ARB_VERSION_V5_MIN 0x50000000
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#define PMIC_ARB_VERSION_V7_MIN 0x70000000
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#define PMIC_ARB_VERSION_V8_MIN 0x80000000
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#define PMIC_ARB_INT_EN 0x0004
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#define PMIC_ARB_FEATURES 0x0004
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#define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)
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#define PMIC_ARB_FEATURES1 0x0008
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#define PMIC_ARB_FEATURES_V8_PERIPH_MASK GENMASK(12, 0)
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/* PMIC Arbiter channel registers offsets */
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#define PMIC_ARB_CMD 0x00
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@ -50,9 +52,11 @@
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#define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
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#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
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#define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
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#define PMIC_ARB_MAX_PPID BIT(13)
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#define PMIC_ARB_APID_VALID BIT(15)
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#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
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#define PMIC_ARB_CHAN_IS_IRQ_OWNER_MASK BIT(24)
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#define PMIC_ARB_V8_CHAN_IS_IRQ_OWNER_MASK BIT(31)
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#define INVALID_EE 0xFF
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/* Ownership Table */
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@ -96,30 +100,37 @@ enum pmic_arb_channel {
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PMIC_ARB_CHANNEL_OBS,
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};
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#define PMIC_ARB_MAX_BUSES 2
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#define PMIC_ARB_MAX_BUSES 4
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/* Maximum number of support PMIC peripherals */
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#define PMIC_ARB_MAX_PERIPHS 512
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#define PMIC_ARB_MAX_PERIPHS_V7 1024
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#define PMIC_ARB_MAX_PERIPHS_V8 8192
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#define PMIC_ARB_TIMEOUT_US 1000
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#define PMIC_ARB_MAX_TRANS_BYTES (8)
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#define PMIC_ARB_APID_MASK 0xFF
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#define PMIC_ARB_PPID_MASK 0xFFF
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#define PMIC_ARB_PPID_MASK GENMASK(11, 0)
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#define PMIC_ARB_V8_PPID_MASK GENMASK(12, 0)
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/* interrupt enable bit */
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#define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
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#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
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((((slave_id) & 0xF) << 28) | \
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(((periph_id) & 0xFF) << 20) | \
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(((irq_id) & 0x7) << 16) | \
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(((apid) & 0x3FF) << 0))
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#define HWIRQ_SID_MASK GENMASK(28, 24)
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#define HWIRQ_PID_MASK GENMASK(23, 16)
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#define HWIRQ_IRQID_MASK GENMASK(15, 13)
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#define HWIRQ_APID_MASK GENMASK(12, 0)
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#define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
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#define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
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#define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
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#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x3FF)
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#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
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(FIELD_PREP(HWIRQ_SID_MASK, (slave_id)) | \
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FIELD_PREP(HWIRQ_PID_MASK, (periph_id)) | \
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FIELD_PREP(HWIRQ_IRQID_MASK, (irq_id)) | \
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FIELD_PREP(HWIRQ_APID_MASK, (apid)))
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#define hwirq_to_sid(hwirq) FIELD_GET(HWIRQ_SID_MASK, (hwirq))
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#define hwirq_to_per(hwirq) FIELD_GET(HWIRQ_PID_MASK, (hwirq))
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#define hwirq_to_irq(hwirq) FIELD_GET(HWIRQ_IRQID_MASK, (hwirq))
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#define hwirq_to_apid(hwirq) FIELD_GET(HWIRQ_APID_MASK, (hwirq))
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struct pmic_arb_ver_ops;
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@ -138,11 +149,12 @@ struct spmi_pmic_arb;
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* @domain: irq domain object for PMIC IRQ domain
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* @intr: address of the SPMI interrupt control registers.
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* @cnfg: address of the PMIC Arbiter configuration registers.
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* @apid_owner: on v8: address of APID owner mapping table registers
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* @spmic: spmi controller registered for this bus
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* @lock: lock to synchronize accesses.
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* @base_apid: on v7: minimum APID associated with the particular SPMI
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* bus instance
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* @apid_count: on v5 and v7: number of APIDs associated with the
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* @base_apid: on v7 and v8: minimum APID associated with the
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* particular SPMI bus instance
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* @apid_count: on v5, v7 and v8: number of APIDs associated with the
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* particular SPMI bus instance
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* @mapping_table: in-memory copy of PPID -> APID mapping table.
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* @mapping_table_valid:bitmap containing valid-only periphs
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@ -159,6 +171,7 @@ struct spmi_pmic_arb_bus {
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struct irq_domain *domain;
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void __iomem *intr;
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void __iomem *cnfg;
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void __iomem *apid_owner;
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struct spmi_controller *spmic;
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raw_spinlock_t lock;
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u16 base_apid;
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@ -181,6 +194,7 @@ struct spmi_pmic_arb_bus {
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* @wr_base: on v1 "core", on v2 "chnls" register base off DT.
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* @core: core register base for v2 and above only (see above)
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* @core_size: core register base size
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* @apid_map: on v8, APID mapping table register base
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* @channel: execution environment channel to use for accesses.
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* @ee: the current Execution Environment
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* @ver_ops: version dependent operations.
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@ -193,6 +207,7 @@ struct spmi_pmic_arb {
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void __iomem *wr_base;
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void __iomem *core;
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resource_size_t core_size;
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void __iomem *apid_map;
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u8 channel;
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u8 ee;
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const struct pmic_arb_ver_ops *ver_ops;
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@ -206,6 +221,7 @@ struct spmi_pmic_arb {
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*
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* @ver_str: version string.
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* @get_core_resources: initializes the core, observer and channels
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* @get_bus_resources: requests per-SPMI bus register resources
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* @init_apid: finds the apid base and count
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* @ppid_to_apid: finds the apid for a given ppid.
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* @non_data_cmd: on v1 issues an spmi non-data command.
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@ -227,6 +243,9 @@ struct spmi_pmic_arb {
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struct pmic_arb_ver_ops {
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const char *ver_str;
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int (*get_core_resources)(struct platform_device *pdev, void __iomem *core);
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int (*get_bus_resources)(struct platform_device *pdev,
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struct device_node *node,
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struct spmi_pmic_arb_bus *bus);
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int (*init_apid)(struct spmi_pmic_arb_bus *bus, int index);
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int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid);
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/* spmi commands (read_cmd, write_cmd, cmd) functionality */
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@ -656,7 +675,7 @@ static int periph_interrupt(struct spmi_pmic_arb_bus *bus, u16 apid)
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unsigned int irq;
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u32 status, id;
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int handled = 0;
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u8 sid = (bus->apid_data[apid].ppid >> 8) & 0xF;
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u8 sid = (bus->apid_data[apid].ppid >> 8) & 0x1F;
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u8 per = bus->apid_data[apid].ppid & 0xFF;
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status = readl_relaxed(pmic_arb->ver_ops->irq_status(bus, apid));
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@ -686,7 +705,7 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
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int last = bus->max_apid;
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/*
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* acc_offset will be non-zero for the secondary SPMI bus instance on
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* v7 controllers.
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* v7 and v8 controllers.
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*/
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int acc_offset = bus->base_apid >> 5;
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u8 ee = pmic_arb->ee;
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@ -913,7 +932,8 @@ static int qpnpint_irq_domain_translate(struct irq_domain *d,
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return -EINVAL;
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if (fwspec->param_count != 4)
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return -EINVAL;
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if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
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if (intspec[0] > FIELD_MAX(HWIRQ_SID_MASK) || intspec[1] > FIELD_MAX(HWIRQ_PID_MASK) ||
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intspec[2] > FIELD_MAX(HWIRQ_IRQID_MASK))
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return -EINVAL;
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ppid = intspec[0] << 8 | intspec[1];
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@ -1160,7 +1180,9 @@ static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb_bus *bus, u16 ppid)
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return apid_valid & ~PMIC_ARB_APID_VALID;
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}
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static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
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static int _pmic_arb_read_apid_map(struct spmi_pmic_arb_bus *bus,
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void __iomem *ppid_base, unsigned long ppid_mask,
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u8 ppid_shift, unsigned long irq_owner_mask)
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{
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struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
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struct apid_data *apidd;
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@ -1171,7 +1193,7 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
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/*
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* In order to allow multiple EEs to write to a single PPID in arbiter
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* version 5 and 7, there is more than one APID mapped to each PPID.
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* version 5,7 and 8, there can be more than one APID mapped to each PPID.
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* The owner field for each of these mappings specifies the EE which is
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* allowed to write to the APID. The owner of the last (highest) APID
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* which has the IRQ owner bit set for a given PPID will receive
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@ -1183,19 +1205,30 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
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* APID = N to N+M-1 are assigned to the secondary bus
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* where N = number of APIDs supported by the primary bus and
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* M = number of APIDs supported by the secondary bus
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*
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* In arbiter version 8, the APID numbering space is divided between
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* the SPMI buses according to this mapping:
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* APID = 0 to N-1 --> bus 0
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* APID = N to N+M-1 --> bus 1
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* APID = N+M to N+M+P-1 --> bus 2
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* APID = N+M+P to N+M+P+Q-1 --> bus 3
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* where N = number of APIDs supported by bus 0
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* M = number of APIDs supported by bus 1
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* P = number of APIDs supported by bus 2
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* Q = number of APIDs supported by bus 3
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*/
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apidd = &bus->apid_data[bus->base_apid];
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apid_max = bus->base_apid + bus->apid_count;
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for (i = bus->base_apid; i < apid_max; i++, apidd++) {
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offset = pmic_arb->ver_ops->apid_map_offset(i);
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if (offset >= pmic_arb->core_size)
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break;
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regval = readl_relaxed(pmic_arb->core + offset);
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regval = readl_relaxed(ppid_base + offset);
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if (!regval)
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continue;
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ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
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is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
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ppid = (regval >> ppid_shift) & ppid_mask;
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is_irq_ee = regval & irq_owner_mask;
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regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, i));
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apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
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@ -1237,6 +1270,12 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
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return 0;
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}
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static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)
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{
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return _pmic_arb_read_apid_map(bus, bus->pmic_arb->core, PMIC_ARB_PPID_MASK,
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8, PMIC_ARB_CHAN_IS_IRQ_OWNER_MASK);
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}
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static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb_bus *bus, u16 ppid)
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{
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if (!(bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
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@ -1345,37 +1384,46 @@ static int pmic_arb_get_core_resources_v7(struct platform_device *pdev,
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return pmic_arb_get_obsrvr_chnls_v2(pdev);
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}
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/*
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* Only v7 supports 2 buses. Each bus will get a different apid count, read
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* from different registers.
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*/
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static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index)
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static int _pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index,
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int max_buses, unsigned long periph_mask)
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{
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struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
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int ret;
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int i;
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if (index == 0) {
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bus->base_apid = 0;
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bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
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PMIC_ARB_FEATURES_PERIPH_MASK;
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} else if (index == 1) {
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bus->base_apid = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &
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PMIC_ARB_FEATURES_PERIPH_MASK;
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bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES1) &
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PMIC_ARB_FEATURES_PERIPH_MASK;
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} else {
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dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n",
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bus->id);
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if (index < 0 || index >= max_buses) {
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dev_err(&bus->spmic->dev, "Unsupported bus index %d detected\n",
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index);
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return -EINVAL;
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}
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if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) {
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dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n",
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bus->base_apid = 0;
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bus->apid_count = 0;
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for (i = 0; i <= index; i++) {
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bus->base_apid += bus->apid_count;
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bus->apid_count = readl_relaxed(pmic_arb->core +
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PMIC_ARB_FEATURES + i * 4) &
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periph_mask;
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}
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if (bus->apid_count == 0) {
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dev_err(&bus->spmic->dev, "Bus %d not implemented\n", index);
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return -EINVAL;
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} else if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) {
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dev_err(&bus->spmic->dev, "Unsupported max APID %d detected\n",
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bus->base_apid + bus->apid_count);
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return -EINVAL;
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}
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ret = pmic_arb_init_apid_min_max(bus);
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return pmic_arb_init_apid_min_max(bus);
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}
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/*
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* Arbiter v7 supports 2 buses. Each bus will get a different apid count, read
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* from different registers.
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*/
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static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index)
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{
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int ret = _pmic_arb_init_apid_v7(bus, index, 2, PMIC_ARB_FEATURES_PERIPH_MASK);
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if (ret)
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return ret;
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@ -1424,6 +1472,102 @@ static int pmic_arb_offset_v7(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
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return offset;
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}
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static int pmic_arb_get_core_resources_v8(struct platform_device *pdev,
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void __iomem *core)
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{
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struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);
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pmic_arb->apid_map = devm_platform_ioremap_resource_byname(pdev, "chnl_map");
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if (IS_ERR(pmic_arb->apid_map))
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return PTR_ERR(pmic_arb->apid_map);
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pmic_arb->core = core;
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pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V8;
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return pmic_arb_get_obsrvr_chnls_v2(pdev);
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}
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static int pmic_arb_get_bus_resources_v8(struct platform_device *pdev,
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struct device_node *node,
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struct spmi_pmic_arb_bus *bus)
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{
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int index;
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index = of_property_match_string(node, "reg-names", "chnl_owner");
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if (index < 0) {
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dev_err(&pdev->dev, "chnl_owner reg region missing\n");
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return -EINVAL;
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}
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bus->apid_owner = devm_of_iomap(&pdev->dev, node, index, NULL);
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return PTR_ERR_OR_ZERO(bus->apid_owner);
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}
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static int pmic_arb_read_apid_map_v8(struct spmi_pmic_arb_bus *bus)
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{
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return _pmic_arb_read_apid_map(bus, bus->pmic_arb->apid_map,
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PMIC_ARB_V8_PPID_MASK, 0,
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PMIC_ARB_V8_CHAN_IS_IRQ_OWNER_MASK);
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}
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/*
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* Arbiter v8 supports up to 4 buses. Each bus will get a different apid count, read
|
||||
* from different registers.
|
||||
*/
|
||||
static int pmic_arb_init_apid_v8(struct spmi_pmic_arb_bus *bus, int index)
|
||||
{
|
||||
int ret = _pmic_arb_init_apid_v7(bus, index, 4,
|
||||
PMIC_ARB_FEATURES_V8_PERIPH_MASK);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pmic_arb_read_apid_map_v8(bus);
|
||||
if (ret) {
|
||||
dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* v8 offset per ee and per apid for observer channels and per apid for
|
||||
* read/write channels.
|
||||
*/
|
||||
static int pmic_arb_offset_v8(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,
|
||||
enum pmic_arb_channel ch_type)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
|
||||
u16 apid;
|
||||
int rc;
|
||||
u32 offset = 0;
|
||||
u16 ppid = (sid << 8) | (addr >> 8);
|
||||
|
||||
rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
apid = rc;
|
||||
switch (ch_type) {
|
||||
case PMIC_ARB_CHANNEL_OBS:
|
||||
offset = 0x40000 * pmic_arb->ee + 0x20 * apid;
|
||||
break;
|
||||
case PMIC_ARB_CHANNEL_RW:
|
||||
if (bus->apid_data[apid].write_ee != pmic_arb->ee) {
|
||||
dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
|
||||
sid, addr);
|
||||
return -EPERM;
|
||||
}
|
||||
offset = 0x200 * apid;
|
||||
break;
|
||||
}
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
|
||||
{
|
||||
return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
|
||||
|
|
@ -1490,6 +1634,14 @@ pmic_arb_acc_enable_v7(struct spmi_pmic_arb_bus *bus, u16 n)
|
|||
return pmic_arb->wr_base + 0x100 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_acc_enable_v8(struct spmi_pmic_arb_bus *bus, u16 n)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
|
||||
|
||||
return pmic_arb->wr_base + 0x100 + 0x200 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_status_v1(struct spmi_pmic_arb_bus *bus, u16 n)
|
||||
{
|
||||
|
|
@ -1516,6 +1668,14 @@ pmic_arb_irq_status_v7(struct spmi_pmic_arb_bus *bus, u16 n)
|
|||
return pmic_arb->wr_base + 0x104 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_status_v8(struct spmi_pmic_arb_bus *bus, u16 n)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
|
||||
|
||||
return pmic_arb->wr_base + 0x104 + 0x200 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_clear_v1(struct spmi_pmic_arb_bus *bus, u16 n)
|
||||
{
|
||||
|
|
@ -1542,6 +1702,14 @@ pmic_arb_irq_clear_v7(struct spmi_pmic_arb_bus *bus, u16 n)
|
|||
return pmic_arb->wr_base + 0x108 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_clear_v8(struct spmi_pmic_arb_bus *bus, u16 n)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;
|
||||
|
||||
return pmic_arb->wr_base + 0x108 + 0x200 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_apid_map_offset_v2(u16 n)
|
||||
{
|
||||
return 0x800 + 0x4 * n;
|
||||
|
|
@ -1557,6 +1725,12 @@ static u32 pmic_arb_apid_map_offset_v7(u16 n)
|
|||
return 0x2000 + 0x4 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_apid_map_offset_v8(u16 n)
|
||||
{
|
||||
/* For v8, offset is from "chnl_map" base register, not "core". */
|
||||
return 0x4 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n)
|
||||
{
|
||||
|
|
@ -1564,7 +1738,7 @@ pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n)
|
|||
}
|
||||
|
||||
/*
|
||||
* For arbiter version 7, APID ownership table registers have independent
|
||||
* For arbiter version 7 and 8, APID ownership table registers have independent
|
||||
* numbering space for each SPMI bus instance, so each is indexed starting from
|
||||
* 0.
|
||||
*/
|
||||
|
|
@ -1574,6 +1748,12 @@ pmic_arb_apid_owner_v7(struct spmi_pmic_arb_bus *bus, u16 n)
|
|||
return bus->cnfg + 0x4 * (n - bus->base_apid);
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_apid_owner_v8(struct spmi_pmic_arb_bus *bus, u16 n)
|
||||
{
|
||||
return bus->apid_owner + 0x4 * (n - bus->base_apid);
|
||||
}
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
|
||||
.ver_str = "v1",
|
||||
.get_core_resources = pmic_arb_get_core_resources_v1,
|
||||
|
|
@ -1654,6 +1834,23 @@ static const struct pmic_arb_ver_ops pmic_arb_v7 = {
|
|||
.apid_owner = pmic_arb_apid_owner_v7,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v8 = {
|
||||
.ver_str = "v8",
|
||||
.get_core_resources = pmic_arb_get_core_resources_v8,
|
||||
.get_bus_resources = pmic_arb_get_bus_resources_v8,
|
||||
.init_apid = pmic_arb_init_apid_v8,
|
||||
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
|
||||
.non_data_cmd = pmic_arb_non_data_cmd_v2,
|
||||
.offset = pmic_arb_offset_v8,
|
||||
.fmt_cmd = pmic_arb_fmt_cmd_v2,
|
||||
.owner_acc_status = pmic_arb_owner_acc_status_v7,
|
||||
.acc_enable = pmic_arb_acc_enable_v8,
|
||||
.irq_status = pmic_arb_irq_status_v8,
|
||||
.irq_clear = pmic_arb_irq_clear_v8,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v8,
|
||||
.apid_owner = pmic_arb_apid_owner_v8,
|
||||
};
|
||||
|
||||
static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
|
||||
.activate = qpnpint_irq_domain_activate,
|
||||
.alloc = qpnpint_irq_domain_alloc,
|
||||
|
|
@ -1731,6 +1928,12 @@ static int spmi_pmic_arb_bus_init(struct platform_device *pdev,
|
|||
bus->spmic = ctrl;
|
||||
bus->id = bus_index;
|
||||
|
||||
if (pmic_arb->ver_ops->get_bus_resources) {
|
||||
ret = pmic_arb->ver_ops->get_bus_resources(pdev, node, bus);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = pmic_arb->ver_ops->init_apid(bus, bus_index);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1825,8 +2028,10 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
pmic_arb->ver_ops = &pmic_arb_v3;
|
||||
else if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
|
||||
pmic_arb->ver_ops = &pmic_arb_v5;
|
||||
else
|
||||
else if (hw_ver < PMIC_ARB_VERSION_V8_MIN)
|
||||
pmic_arb->ver_ops = &pmic_arb_v7;
|
||||
else
|
||||
pmic_arb->ver_ops = &pmic_arb_v8;
|
||||
|
||||
err = pmic_arb->ver_ops->get_core_resources(pdev, core);
|
||||
if (err)
|
||||
|
|
@ -1875,6 +2080,7 @@ static void spmi_pmic_arb_remove(struct platform_device *pdev)
|
|||
static const struct of_device_id spmi_pmic_arb_match_table[] = {
|
||||
{ .compatible = "qcom,spmi-pmic-arb", },
|
||||
{ .compatible = "qcom,x1e80100-spmi-pmic-arb", },
|
||||
{ .compatible = "qcom,glymur-spmi-pmic-arb", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue