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drm/i915/dram: Fix ICL DIMM_S decoding
Unfortunately the MAD_DIMM DIMM_S and DIMM_L bits on ICL are not idential, so we are currently decoding DIMM_S incorrectly. Fix the problem by defining the DIMM_S and DIMM_L bits separately. And for consistency do that same for SKL, even though there the bits do match between the two DIMMs. The result is rather repetitive in places, but I didn't feel like obfuscatign things with cpp macros/etc. Broken decoding on Dell XPS 13 7390 2-in-1: CH0 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 DIMM S size: 32 Gb, width: X32, ranks: 3, 16Gb+ DIMMs: no CH0 ranks: 2, 16Gb+ DIMMs: no CH1 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 DIMM S size: 32 Gb, width: X32, ranks: 3, 16Gb+ DIMMs: no CH1 ranks: 2, 16Gb+ DIMMs: no Memory configuration is symmetric? no Fixed decoding on Dell XPS 13 7390 2-in-1: CH0 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 DIMM S size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 ranks: 2, 16Gb+ DIMMs: no CH1 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 DIMM S size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 ranks: 2, 16Gb+ DIMMs: no Memory configuration is symmetric? yes Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029204215.12292-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
parent
8c171a9b8c
commit
7e2d785354
2 changed files with 155 additions and 64 deletions
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@ -160,25 +160,40 @@
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#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
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#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
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#define SKL_DRAM_S_SHIFT 16
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#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10)
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#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0)
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#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1)
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#define SKL_DRAM_WIDTH_MASK REG_GENMASK(9, 8)
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#define SKL_DRAM_WIDTH_X8 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 0)
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#define SKL_DRAM_WIDTH_X16 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 1)
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#define SKL_DRAM_WIDTH_X32 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 2)
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#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0)
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#define ICL_DRAM_RANK_MASK REG_GENMASK(10, 9)
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#define ICL_DRAM_RANK_1 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 0)
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#define ICL_DRAM_RANK_2 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 1)
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#define ICL_DRAM_RANK_3 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 2)
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#define ICL_DRAM_RANK_4 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 3)
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#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7)
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#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0)
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#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1)
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#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2)
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#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0)
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#define SKL_DIMM_S_RANK_MASK REG_GENMASK(26, 26)
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#define SKL_DIMM_S_RANK_1 REG_FIELD_PREP(SKL_DIMM_S_RANK_MASK, 0)
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#define SKL_DIMM_S_RANK_2 REG_FIELD_PREP(SKL_DIMM_S_RANK_MASK, 1)
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#define SKL_DIMM_S_WIDTH_MASK REG_GENMASK(25, 24)
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#define SKL_DIMM_S_WIDTH_X8 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 0)
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#define SKL_DIMM_S_WIDTH_X16 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 1)
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#define SKL_DIMM_S_WIDTH_X32 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 2)
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#define SKL_DIMM_S_SIZE_MASK REG_GENMASK(21, 16)
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#define SKL_DIMM_L_RANK_MASK REG_GENMASK(10, 10)
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#define SKL_DIMM_L_RANK_1 REG_FIELD_PREP(SKL_DIMM_L_RANK_MASK, 0)
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#define SKL_DIMM_L_RANK_2 REG_FIELD_PREP(SKL_DIMM_L_RANK_MASK, 1)
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#define SKL_DIMM_L_WIDTH_MASK REG_GENMASK(9, 8)
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#define SKL_DIMM_L_WIDTH_X8 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 0)
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#define SKL_DIMM_L_WIDTH_X16 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 1)
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#define SKL_DIMM_L_WIDTH_X32 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 2)
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#define SKL_DIMM_L_SIZE_MASK REG_GENMASK(5, 0)
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#define ICL_DIMM_S_RANK_MASK REG_GENMASK(27, 26)
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#define ICL_DIMM_S_RANK_1 REG_FIELD_PREP(ICL_DIMM_S_RANK_MASK, 0)
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#define ICL_DIMM_S_RANK_2 REG_FIELD_PREP(ICL_DIMM_S_RANK_MASK, 1)
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#define ICL_DIMM_S_WIDTH_MASK REG_GENMASK(25, 24)
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#define ICL_DIMM_S_WIDTH_X8 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 0)
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#define ICL_DIMM_S_WIDTH_X16 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 1)
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#define ICL_DIMM_S_WIDTH_X32 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 2)
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#define ICL_DIMM_S_SIZE_MASK REG_GENMASK(22, 16)
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#define ICL_DIMM_L_RANK_MASK REG_GENMASK(10, 9)
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#define ICL_DIMM_L_RANK_1 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 0)
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#define ICL_DIMM_L_RANK_2 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 1)
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#define ICL_DIMM_L_RANK_3 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 2)
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#define ICL_DIMM_L_RANK_4 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 3)
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#define ICL_DIMM_L_WIDTH_MASK REG_GENMASK(8, 7)
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#define ICL_DIMM_L_WIDTH_X8 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 0)
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#define ICL_DIMM_L_WIDTH_X16 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 1)
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#define ICL_DIMM_L_WIDTH_X32 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 2)
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#define ICL_DIMM_L_SIZE_MASK REG_GENMASK(6, 0)
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#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
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#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
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@ -267,69 +267,121 @@ static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
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}
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/* Returns total Gb for the whole DIMM */
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static int skl_get_dimm_size(u16 val)
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static int skl_get_dimm_s_size(u32 val)
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{
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return REG_FIELD_GET(SKL_DRAM_SIZE_MASK, val) * 8;
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return REG_FIELD_GET(SKL_DIMM_S_SIZE_MASK, val) * 8;
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}
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static int skl_get_dimm_width(u16 val)
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static int skl_get_dimm_l_size(u32 val)
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{
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if (skl_get_dimm_size(val) == 0)
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return REG_FIELD_GET(SKL_DIMM_L_SIZE_MASK, val) * 8;
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}
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static int skl_get_dimm_s_width(u32 val)
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{
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if (skl_get_dimm_s_size(val) == 0)
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return 0;
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switch (val & SKL_DRAM_WIDTH_MASK) {
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case SKL_DRAM_WIDTH_X8:
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case SKL_DRAM_WIDTH_X16:
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case SKL_DRAM_WIDTH_X32:
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val = REG_FIELD_GET(SKL_DRAM_WIDTH_MASK, val);
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return 8 << val;
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switch (val & SKL_DIMM_S_WIDTH_MASK) {
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case SKL_DIMM_S_WIDTH_X8:
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case SKL_DIMM_S_WIDTH_X16:
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case SKL_DIMM_S_WIDTH_X32:
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return 8 << REG_FIELD_GET(SKL_DIMM_S_WIDTH_MASK, val);
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default:
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MISSING_CASE(val);
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return 0;
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}
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}
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static int skl_get_dimm_ranks(u16 val)
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static int skl_get_dimm_l_width(u32 val)
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{
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if (skl_get_dimm_size(val) == 0)
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if (skl_get_dimm_l_size(val) == 0)
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return 0;
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val = REG_FIELD_GET(SKL_DRAM_RANK_MASK, val);
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switch (val & SKL_DIMM_L_WIDTH_MASK) {
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case SKL_DIMM_L_WIDTH_X8:
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case SKL_DIMM_L_WIDTH_X16:
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case SKL_DIMM_L_WIDTH_X32:
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return 8 << REG_FIELD_GET(SKL_DIMM_L_WIDTH_MASK, val);
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default:
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MISSING_CASE(val);
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return 0;
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}
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}
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return val + 1;
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static int skl_get_dimm_s_ranks(u32 val)
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{
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if (skl_get_dimm_s_size(val) == 0)
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return 0;
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return REG_FIELD_GET(SKL_DIMM_S_RANK_MASK, val) + 1;
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}
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static int skl_get_dimm_l_ranks(u32 val)
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{
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if (skl_get_dimm_l_size(val) == 0)
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return 0;
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return REG_FIELD_GET(SKL_DIMM_L_RANK_MASK, val) + 1;
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}
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/* Returns total Gb for the whole DIMM */
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static int icl_get_dimm_size(u16 val)
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static int icl_get_dimm_s_size(u32 val)
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{
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return REG_FIELD_GET(ICL_DRAM_SIZE_MASK, val) * 8 / 2;
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return REG_FIELD_GET(ICL_DIMM_S_SIZE_MASK, val) * 8 / 2;
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}
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static int icl_get_dimm_width(u16 val)
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static int icl_get_dimm_l_size(u32 val)
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{
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if (icl_get_dimm_size(val) == 0)
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return REG_FIELD_GET(ICL_DIMM_L_SIZE_MASK, val) * 8 / 2;
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}
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static int icl_get_dimm_s_width(u32 val)
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{
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if (icl_get_dimm_s_size(val) == 0)
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return 0;
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switch (val & ICL_DRAM_WIDTH_MASK) {
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case ICL_DRAM_WIDTH_X8:
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case ICL_DRAM_WIDTH_X16:
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case ICL_DRAM_WIDTH_X32:
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val = REG_FIELD_GET(ICL_DRAM_WIDTH_MASK, val);
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return 8 << val;
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switch (val & ICL_DIMM_S_WIDTH_MASK) {
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case ICL_DIMM_S_WIDTH_X8:
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case ICL_DIMM_S_WIDTH_X16:
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case ICL_DIMM_S_WIDTH_X32:
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return 8 << REG_FIELD_GET(ICL_DIMM_S_WIDTH_MASK, val);
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default:
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MISSING_CASE(val);
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return 0;
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}
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}
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static int icl_get_dimm_ranks(u16 val)
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static int icl_get_dimm_l_width(u32 val)
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{
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if (icl_get_dimm_size(val) == 0)
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if (icl_get_dimm_l_size(val) == 0)
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return 0;
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val = REG_FIELD_GET(ICL_DRAM_RANK_MASK, val);
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switch (val & ICL_DIMM_L_WIDTH_MASK) {
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case ICL_DIMM_L_WIDTH_X8:
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case ICL_DIMM_L_WIDTH_X16:
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case ICL_DIMM_L_WIDTH_X32:
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return 8 << REG_FIELD_GET(ICL_DIMM_L_WIDTH_MASK, val);
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default:
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MISSING_CASE(val);
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return 0;
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}
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}
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return val + 1;
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static int icl_get_dimm_s_ranks(u32 val)
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{
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if (icl_get_dimm_s_size(val) == 0)
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return 0;
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return REG_FIELD_GET(ICL_DIMM_S_RANK_MASK, val) + 1;
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}
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static int icl_get_dimm_l_ranks(u32 val)
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{
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if (icl_get_dimm_l_size(val) == 0)
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return 0;
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return REG_FIELD_GET(ICL_DIMM_L_RANK_MASK, val) + 1;
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}
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static bool
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@ -340,35 +392,59 @@ skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
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}
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static void
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skl_dram_get_dimm_info(struct drm_i915_private *i915,
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struct dram_dimm_info *dimm,
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int channel, char dimm_name, u16 val)
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skl_dram_print_dimm_info(struct drm_i915_private *i915,
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struct dram_dimm_info *dimm,
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int channel, char dimm_name)
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{
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if (GRAPHICS_VER(i915) >= 11) {
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dimm->size = icl_get_dimm_size(val);
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dimm->width = icl_get_dimm_width(val);
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dimm->ranks = icl_get_dimm_ranks(val);
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} else {
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dimm->size = skl_get_dimm_size(val);
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dimm->width = skl_get_dimm_width(val);
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dimm->ranks = skl_get_dimm_ranks(val);
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}
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drm_dbg_kms(&i915->drm,
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"CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb+ DIMMs: %s\n",
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channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
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str_yes_no(skl_is_16gb_dimm(dimm)));
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}
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static void
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skl_dram_get_dimm_l_info(struct drm_i915_private *i915,
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struct dram_dimm_info *dimm,
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int channel, u32 val)
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{
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if (GRAPHICS_VER(i915) >= 11) {
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dimm->size = icl_get_dimm_l_size(val);
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dimm->width = icl_get_dimm_l_width(val);
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dimm->ranks = icl_get_dimm_l_ranks(val);
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} else {
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dimm->size = skl_get_dimm_l_size(val);
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dimm->width = skl_get_dimm_l_width(val);
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dimm->ranks = skl_get_dimm_l_ranks(val);
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}
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skl_dram_print_dimm_info(i915, dimm, channel, 'L');
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}
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static void
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skl_dram_get_dimm_s_info(struct drm_i915_private *i915,
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struct dram_dimm_info *dimm,
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int channel, u32 val)
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{
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if (GRAPHICS_VER(i915) >= 11) {
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dimm->size = icl_get_dimm_s_size(val);
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dimm->width = icl_get_dimm_s_width(val);
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dimm->ranks = icl_get_dimm_s_ranks(val);
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} else {
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dimm->size = skl_get_dimm_s_size(val);
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dimm->width = skl_get_dimm_s_width(val);
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dimm->ranks = skl_get_dimm_s_ranks(val);
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}
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skl_dram_print_dimm_info(i915, dimm, channel, 'S');
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}
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static int
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skl_dram_get_channel_info(struct drm_i915_private *i915,
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struct dram_channel_info *ch,
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int channel, u32 val)
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{
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skl_dram_get_dimm_info(i915, &ch->dimm_l,
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channel, 'L', val & 0xffff);
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skl_dram_get_dimm_info(i915, &ch->dimm_s,
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channel, 'S', val >> 16);
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skl_dram_get_dimm_l_info(i915, &ch->dimm_l, channel, val);
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skl_dram_get_dimm_s_info(i915, &ch->dimm_s, channel, val);
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if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
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drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
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