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LoongArch: Adjust common macro definitions for 32BIT/64BIT
Most common macros are defined in asm.h, asmmacro.h and stackframe.h. Adjust these macros for both 32BIT and 64BIT. Add SETUP_TWINS (Setup Trampoline Windows) and SETUP_MODES (Setup CRMD/ PRMD/EUEN) which will be used later. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Huacai Chen
parent
81f5d15c48
commit
708ed32c84
3 changed files with 174 additions and 55 deletions
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@ -72,11 +72,11 @@
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#define INT_SUB sub.w
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#define INT_L ld.w
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#define INT_S st.w
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#define INT_SLL slli.w
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#define INT_SLLI slli.w
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#define INT_SLLV sll.w
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#define INT_SRL srli.w
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#define INT_SRLI srli.w
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#define INT_SRLV srl.w
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#define INT_SRA srai.w
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#define INT_SRAI srai.w
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#define INT_SRAV sra.w
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#endif
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@ -86,11 +86,11 @@
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#define INT_SUB sub.d
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#define INT_L ld.d
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#define INT_S st.d
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#define INT_SLL slli.d
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#define INT_SLLI slli.d
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#define INT_SLLV sll.d
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#define INT_SRL srli.d
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#define INT_SRLI srli.d
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#define INT_SRLV srl.d
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#define INT_SRA srai.d
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#define INT_SRAI srai.d
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#define INT_SRAV sra.d
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#endif
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@ -100,15 +100,23 @@
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#if (__SIZEOF_LONG__ == 4)
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#define LONG_ADD add.w
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#define LONG_ADDI addi.w
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#define LONG_ALSL alsl.w
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#define LONG_BSTRINS bstrins.w
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#define LONG_BSTRPICK bstrpick.w
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#define LONG_SUB sub.w
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#define LONG_L ld.w
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#define LONG_LI li.w
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#define LONG_LPTR ld.w
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#define LONG_S st.w
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#define LONG_SLL slli.w
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#define LONG_SPTR st.w
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#define LONG_SLLI slli.w
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#define LONG_SLLV sll.w
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#define LONG_SRL srli.w
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#define LONG_SRLI srli.w
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#define LONG_SRLV srl.w
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#define LONG_SRA srai.w
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#define LONG_SRAI srai.w
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#define LONG_SRAV sra.w
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#define LONG_ROTR rotr.w
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#define LONG_ROTRI rotri.w
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#ifdef __ASSEMBLER__
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#define LONG .word
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@ -121,15 +129,23 @@
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#if (__SIZEOF_LONG__ == 8)
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#define LONG_ADD add.d
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#define LONG_ADDI addi.d
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#define LONG_ALSL alsl.d
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#define LONG_BSTRINS bstrins.d
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#define LONG_BSTRPICK bstrpick.d
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#define LONG_SUB sub.d
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#define LONG_L ld.d
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#define LONG_LI li.d
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#define LONG_LPTR ldptr.d
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#define LONG_S st.d
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#define LONG_SLL slli.d
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#define LONG_SPTR stptr.d
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#define LONG_SLLI slli.d
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#define LONG_SLLV sll.d
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#define LONG_SRL srli.d
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#define LONG_SRLI srli.d
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#define LONG_SRLV srl.d
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#define LONG_SRA srai.d
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#define LONG_SRAI srai.d
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#define LONG_SRAV sra.d
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#define LONG_ROTR rotr.d
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#define LONG_ROTRI rotri.d
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#ifdef __ASSEMBLER__
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#define LONG .dword
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@ -145,16 +161,23 @@
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#if (__SIZEOF_POINTER__ == 4)
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#define PTR_ADD add.w
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#define PTR_ADDI addi.w
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#define PTR_ALSL alsl.w
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#define PTR_BSTRINS bstrins.w
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#define PTR_BSTRPICK bstrpick.w
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#define PTR_SUB sub.w
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#define PTR_L ld.w
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#define PTR_S st.w
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#define PTR_LI li.w
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#define PTR_SLL slli.w
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#define PTR_LPTR ld.w
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#define PTR_S st.w
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#define PTR_SPTR st.w
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#define PTR_SLLI slli.w
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#define PTR_SLLV sll.w
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#define PTR_SRL srli.w
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#define PTR_SRLI srli.w
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#define PTR_SRLV srl.w
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#define PTR_SRA srai.w
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#define PTR_SRAI srai.w
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#define PTR_SRAV sra.w
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#define PTR_ROTR rotr.w
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#define PTR_ROTRI rotri.w
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#define PTR_SCALESHIFT 2
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@ -168,16 +191,23 @@
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#if (__SIZEOF_POINTER__ == 8)
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#define PTR_ADD add.d
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#define PTR_ADDI addi.d
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#define PTR_ALSL alsl.d
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#define PTR_BSTRINS bstrins.d
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#define PTR_BSTRPICK bstrpick.d
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#define PTR_SUB sub.d
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#define PTR_L ld.d
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#define PTR_S st.d
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#define PTR_LI li.d
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#define PTR_SLL slli.d
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#define PTR_LPTR ldptr.d
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#define PTR_S st.d
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#define PTR_SPTR stptr.d
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#define PTR_SLLI slli.d
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#define PTR_SLLV sll.d
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#define PTR_SRL srli.d
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#define PTR_SRLI srli.d
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#define PTR_SRLV srl.d
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#define PTR_SRA srai.d
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#define PTR_SRAI srai.d
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#define PTR_SRAV sra.d
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#define PTR_ROTR rotr.d
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#define PTR_ROTRI rotri.d
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#define PTR_SCALESHIFT 3
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@ -190,10 +220,17 @@
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/* Annotate a function as being unsuitable for kprobes. */
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#ifdef CONFIG_KPROBES
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#ifdef CONFIG_32BIT
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#define _ASM_NOKPROBE(name) \
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.pushsection "_kprobe_blacklist", "aw"; \
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.long name; \
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.popsection
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#else
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#define _ASM_NOKPROBE(name) \
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.pushsection "_kprobe_blacklist", "aw"; \
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.quad name; \
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.popsection
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#endif
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#else
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#define _ASM_NOKPROBE(name)
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#endif
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@ -5,43 +5,55 @@
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#ifndef _ASM_ASMMACRO_H
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#define _ASM_ASMMACRO_H
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#include <linux/sizes.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#include <asm/fpregdef.h>
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#include <asm/loongarch.h>
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#ifdef CONFIG_64BIT
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#define TASK_STRUCT_OFFSET 0
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#else
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#define TASK_STRUCT_OFFSET 2000
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#endif
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.macro cpu_save_nonscratch thread
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stptr.d s0, \thread, THREAD_REG23
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stptr.d s1, \thread, THREAD_REG24
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stptr.d s2, \thread, THREAD_REG25
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stptr.d s3, \thread, THREAD_REG26
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stptr.d s4, \thread, THREAD_REG27
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stptr.d s5, \thread, THREAD_REG28
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stptr.d s6, \thread, THREAD_REG29
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stptr.d s7, \thread, THREAD_REG30
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stptr.d s8, \thread, THREAD_REG31
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stptr.d sp, \thread, THREAD_REG03
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stptr.d fp, \thread, THREAD_REG22
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LONG_SPTR s0, \thread, (THREAD_REG23 - TASK_STRUCT_OFFSET)
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LONG_SPTR s1, \thread, (THREAD_REG24 - TASK_STRUCT_OFFSET)
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LONG_SPTR s2, \thread, (THREAD_REG25 - TASK_STRUCT_OFFSET)
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LONG_SPTR s3, \thread, (THREAD_REG26 - TASK_STRUCT_OFFSET)
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LONG_SPTR s4, \thread, (THREAD_REG27 - TASK_STRUCT_OFFSET)
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LONG_SPTR s5, \thread, (THREAD_REG28 - TASK_STRUCT_OFFSET)
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LONG_SPTR s6, \thread, (THREAD_REG29 - TASK_STRUCT_OFFSET)
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LONG_SPTR s7, \thread, (THREAD_REG30 - TASK_STRUCT_OFFSET)
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LONG_SPTR s8, \thread, (THREAD_REG31 - TASK_STRUCT_OFFSET)
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LONG_SPTR ra, \thread, (THREAD_REG01 - TASK_STRUCT_OFFSET)
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LONG_SPTR sp, \thread, (THREAD_REG03 - TASK_STRUCT_OFFSET)
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LONG_SPTR fp, \thread, (THREAD_REG22 - TASK_STRUCT_OFFSET)
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.endm
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.macro cpu_restore_nonscratch thread
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ldptr.d s0, \thread, THREAD_REG23
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ldptr.d s1, \thread, THREAD_REG24
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ldptr.d s2, \thread, THREAD_REG25
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ldptr.d s3, \thread, THREAD_REG26
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ldptr.d s4, \thread, THREAD_REG27
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ldptr.d s5, \thread, THREAD_REG28
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ldptr.d s6, \thread, THREAD_REG29
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ldptr.d s7, \thread, THREAD_REG30
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ldptr.d s8, \thread, THREAD_REG31
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ldptr.d ra, \thread, THREAD_REG01
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ldptr.d sp, \thread, THREAD_REG03
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ldptr.d fp, \thread, THREAD_REG22
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LONG_LPTR s0, \thread, (THREAD_REG23 - TASK_STRUCT_OFFSET)
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LONG_LPTR s1, \thread, (THREAD_REG24 - TASK_STRUCT_OFFSET)
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LONG_LPTR s2, \thread, (THREAD_REG25 - TASK_STRUCT_OFFSET)
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LONG_LPTR s3, \thread, (THREAD_REG26 - TASK_STRUCT_OFFSET)
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LONG_LPTR s4, \thread, (THREAD_REG27 - TASK_STRUCT_OFFSET)
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LONG_LPTR s5, \thread, (THREAD_REG28 - TASK_STRUCT_OFFSET)
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LONG_LPTR s6, \thread, (THREAD_REG29 - TASK_STRUCT_OFFSET)
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LONG_LPTR s7, \thread, (THREAD_REG30 - TASK_STRUCT_OFFSET)
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LONG_LPTR s8, \thread, (THREAD_REG31 - TASK_STRUCT_OFFSET)
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LONG_LPTR ra, \thread, (THREAD_REG01 - TASK_STRUCT_OFFSET)
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LONG_LPTR sp, \thread, (THREAD_REG03 - TASK_STRUCT_OFFSET)
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LONG_LPTR fp, \thread, (THREAD_REG22 - TASK_STRUCT_OFFSET)
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.endm
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.macro fpu_save_csr thread tmp
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movfcsr2gr \tmp, fcsr0
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#ifdef CONFIG_32BIT
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st.w \tmp, \thread, THREAD_FCSR
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#else
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stptr.w \tmp, \thread, THREAD_FCSR
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#endif
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#ifdef CONFIG_CPU_HAS_LBT
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/* TM bit is always 0 if LBT not supported */
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andi \tmp, \tmp, FPU_CSR_TM
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@ -56,7 +68,11 @@
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.endm
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.macro fpu_restore_csr thread tmp0 tmp1
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#ifdef CONFIG_32BIT
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ld.w \tmp0, \thread, THREAD_FCSR
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#else
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ldptr.w \tmp0, \thread, THREAD_FCSR
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#endif
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movgr2fcsr fcsr0, \tmp0
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#ifdef CONFIG_CPU_HAS_LBT
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/* TM bit is always 0 if LBT not supported */
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@ -88,9 +104,52 @@
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#endif
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.endm
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#ifdef CONFIG_32BIT
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.macro fpu_save_cc thread tmp0 tmp1
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movcf2gr \tmp0, $fcc0
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move \tmp1, \tmp0
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move \tmp1, \tmp0
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movcf2gr \tmp0, $fcc1
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bstrins.w \tmp1, \tmp0, 15, 8
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movcf2gr \tmp0, $fcc2
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bstrins.w \tmp1, \tmp0, 23, 16
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movcf2gr \tmp0, $fcc3
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bstrins.w \tmp1, \tmp0, 31, 24
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st.w \tmp1, \thread, THREAD_FCC
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movcf2gr \tmp0, $fcc4
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move \tmp1, \tmp0
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movcf2gr \tmp0, $fcc5
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bstrins.w \tmp1, \tmp0, 15, 8
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movcf2gr \tmp0, $fcc6
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bstrins.w \tmp1, \tmp0, 23, 16
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movcf2gr \tmp0, $fcc7
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bstrins.w \tmp1, \tmp0, 31, 24
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st.w \tmp1, \thread, (THREAD_FCC + 4)
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.endm
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.macro fpu_restore_cc thread tmp0 tmp1
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ld.w \tmp0, \thread, THREAD_FCC
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bstrpick.w \tmp1, \tmp0, 7, 0
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movgr2cf $fcc0, \tmp1
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bstrpick.w \tmp1, \tmp0, 15, 8
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movgr2cf $fcc1, \tmp1
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bstrpick.w \tmp1, \tmp0, 23, 16
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movgr2cf $fcc2, \tmp1
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bstrpick.w \tmp1, \tmp0, 31, 24
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movgr2cf $fcc3, \tmp1
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ld.w \tmp0, \thread, (THREAD_FCC + 4)
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bstrpick.w \tmp1, \tmp0, 7, 0
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movgr2cf $fcc4, \tmp1
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bstrpick.w \tmp1, \tmp0, 15, 8
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movgr2cf $fcc5, \tmp1
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bstrpick.w \tmp1, \tmp0, 23, 16
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movgr2cf $fcc6, \tmp1
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bstrpick.w \tmp1, \tmp0, 31, 24
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movgr2cf $fcc7, \tmp1
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.endm
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#else
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.macro fpu_save_cc thread tmp0 tmp1
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movcf2gr \tmp0, $fcc0
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move \tmp1, \tmp0
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movcf2gr \tmp0, $fcc1
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bstrins.d \tmp1, \tmp0, 15, 8
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movcf2gr \tmp0, $fcc2
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@ -109,7 +168,7 @@
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.endm
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.macro fpu_restore_cc thread tmp0 tmp1
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ldptr.d \tmp0, \thread, THREAD_FCC
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ldptr.d \tmp0, \thread, THREAD_FCC
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bstrpick.d \tmp1, \tmp0, 7, 0
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movgr2cf $fcc0, \tmp1
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bstrpick.d \tmp1, \tmp0, 15, 8
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@ -127,6 +186,7 @@
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bstrpick.d \tmp1, \tmp0, 63, 56
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movgr2cf $fcc7, \tmp1
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.endm
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#endif
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.macro fpu_save_double thread tmp
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li.w \tmp, THREAD_FPR0
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@ -606,12 +666,14 @@
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766:
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lu12i.w \reg, 0
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ori \reg, \reg, 0
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#ifdef CONFIG_64BIT
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lu32i.d \reg, 0
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lu52i.d \reg, \reg, 0
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#endif
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.pushsection ".la_abs", "aw", %progbits
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.p2align 3
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.dword 766b
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.dword \sym
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.p2align PTRLOG
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PTR 766b
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PTR \sym
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.popsection
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#endif
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.endm
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@ -38,22 +38,42 @@
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cfi_restore \reg \offset \docfi
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.endm
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.macro SETUP_TWINS temp
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pcaddi t0, 0
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PTR_LI t1, ~TO_PHYS_MASK
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and t0, t0, t1
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ori t0, t0, (1 << 4 | 1)
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csrwr t0, LOONGARCH_CSR_DMWIN0
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PTR_LI t0, CSR_DMW1_INIT
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csrwr t0, LOONGARCH_CSR_DMWIN1
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.endm
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.macro SETUP_MODES temp
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/* Enable PG */
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li.w \temp, 0xb0 # PLV=0, IE=0, PG=1
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csrwr \temp, LOONGARCH_CSR_CRMD
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li.w \temp, 0x04 # PLV=0, PIE=1, PWE=0
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csrwr \temp, LOONGARCH_CSR_PRMD
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li.w \temp, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
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csrwr \temp, LOONGARCH_CSR_EUEN
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.endm
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.macro SETUP_DMWINS temp
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li.d \temp, CSR_DMW0_INIT # WUC, PLV0, 0x8000 xxxx xxxx xxxx
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PTR_LI \temp, CSR_DMW0_INIT # SUC, PLV0, LA32: 0x8xxx xxxx, LA64: 0x8000 xxxx xxxx xxxx
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csrwr \temp, LOONGARCH_CSR_DMWIN0
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li.d \temp, CSR_DMW1_INIT # CAC, PLV0, 0x9000 xxxx xxxx xxxx
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PTR_LI \temp, CSR_DMW1_INIT # CAC, PLV0, LA32: 0xaxxx xxxx, LA64: 0x9000 xxxx xxxx xxxx
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csrwr \temp, LOONGARCH_CSR_DMWIN1
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li.d \temp, CSR_DMW2_INIT # WUC, PLV0, 0xa000 xxxx xxxx xxxx
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PTR_LI \temp, CSR_DMW2_INIT # WUC, PLV0, LA32: unavailable, LA64: 0xa000 xxxx xxxx xxxx
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csrwr \temp, LOONGARCH_CSR_DMWIN2
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li.d \temp, CSR_DMW3_INIT # 0x0, unused
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PTR_LI \temp, CSR_DMW3_INIT # 0x0, unused
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csrwr \temp, LOONGARCH_CSR_DMWIN3
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.endm
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/* Jump to the runtime virtual address. */
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.macro JUMP_VIRT_ADDR temp1 temp2
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li.d \temp1, CACHE_BASE
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PTR_LI \temp1, CACHE_BASE
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pcaddi \temp2, 0
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bstrins.d \temp1, \temp2, (DMW_PABITS - 1), 0
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PTR_BSTRINS \temp1, \temp2, (DMW_PABITS - 1), 0
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jirl zero, \temp1, 0xc
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.endm
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@ -171,7 +191,7 @@
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andi t0, t0, 0x3 /* extract pplv bit */
|
||||
beqz t0, 9f
|
||||
|
||||
li.d tp, ~_THREAD_MASK
|
||||
LONG_LI tp, ~_THREAD_MASK
|
||||
and tp, tp, sp
|
||||
cfi_st u0, PT_R21, \docfi
|
||||
csrrd u0, PERCPU_BASE_KS
|
||||
|
|
|
|||
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Add table
Add a link
Reference in a new issue