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drm/amdgpu: update userqueue BOs and PDs
This patch updates the VM_IOCTL to allow userspace to synchronize the mapping/unmapping of a BO in the page table. The major changes are: - it adds a drm_timeline object as an input parameter to the VM IOCTL. - this object is used by the kernel to sync the update of the BO in the page table during the mapping of the object. - the kernel also synchronizes the tlb flush of the page table entry of this object during the unmapping (Added in this series: https://patchwork.freedesktop.org/series/131276/ and https://patchwork.freedesktop.org/patch/584182/) - the userspace can wait on this timeline, and then the BO is ready to be consumed by the GPU. The UAPI for the same has been approved here: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/392 V2: - remove the eviction fence coupling V3: - added the drm timeline support instead of input/output fence (Christian) V4: - made timeline 64-bit (Christian) - bug fix (Arvind) V5: GLCTS bug fix (Arvind) V6: Rename syncobj_handle -> timeline_syncobj_out Rename point -> timeline_point_in (Marek) V7: Addressed review comments from Christian: - do not send last_update fence in case of vm_clear_freed, instead return the fence from gen_va_update_vm - move the functions to update bo_mapping to amdgpu_gem.c - do not use amdgpu_userq_update_vm anymore in userq_create() V8: Addressed review comments from Christian: - Split amdgpu_gem_update_bo_mapping function. - amdgpu_gem_va_update_vm should return stub for error. V9: Addressed review comments from Christian: - Rename the function amdgpu_gem_update_timeline_node. - amdgpu_gem_update_timeline_node should be void function. - when timeline_point is zero don't allocate a chain and call drm_syncobj_replace_fence() instead of drm_syncobj_add_point(). V11: rebase V12: Fix 32-bit holes issue in sturct drm_amdgpu_gem_va. V13: Fix the review comment by renaming timeline syncobj (Marek) Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Felix Kuehling <felix.kuehling@amd.com> Cc: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Arvind Yadav
Alex Deucher
parent
8949843762
commit
70773bef4e
2 changed files with 113 additions and 9 deletions
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@ -36,6 +36,7 @@
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#include <drm/drm_exec.h>
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#include <drm/drm_gem_ttm_helper.h>
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#include <drm/ttm/ttm_tt.h>
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#include <drm/drm_syncobj.h>
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#include "amdgpu.h"
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#include "amdgpu_display.h"
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@ -44,6 +45,75 @@
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#include "amdgpu_xgmi.h"
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#include "amdgpu_vm.h"
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static int
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amdgpu_gem_update_timeline_node(struct drm_file *filp,
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uint32_t syncobj_handle,
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uint64_t point,
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struct drm_syncobj **syncobj,
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struct dma_fence_chain **chain)
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{
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if (!syncobj_handle)
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return 0;
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/* Find the sync object */
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*syncobj = drm_syncobj_find(filp, syncobj_handle);
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if (!*syncobj)
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return -ENOENT;
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if (!point)
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return 0;
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/* Allocate the chain node */
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*chain = dma_fence_chain_alloc();
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if (!*chain) {
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drm_syncobj_put(*syncobj);
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return -ENOMEM;
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}
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return 0;
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}
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static void
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amdgpu_gem_update_bo_mapping(struct drm_file *filp,
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struct amdgpu_bo_va *bo_va,
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uint32_t operation,
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uint64_t point,
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struct dma_fence *fence,
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struct drm_syncobj *syncobj,
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struct dma_fence_chain *chain)
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{
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struct amdgpu_bo *bo = bo_va ? bo_va->base.bo : NULL;
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struct amdgpu_fpriv *fpriv = filp->driver_priv;
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struct amdgpu_vm *vm = &fpriv->vm;
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struct dma_fence *last_update;
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if (!syncobj)
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return;
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/* Find the last update fence */
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switch (operation) {
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case AMDGPU_VA_OP_MAP:
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case AMDGPU_VA_OP_REPLACE:
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if (bo && (bo->tbo.base.resv == vm->root.bo->tbo.base.resv))
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last_update = vm->last_update;
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else
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last_update = bo_va->last_pt_update;
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break;
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case AMDGPU_VA_OP_UNMAP:
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case AMDGPU_VA_OP_CLEAR:
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last_update = fence;
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break;
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default:
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return;
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}
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/* Add fence to timeline */
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if (!point)
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drm_syncobj_replace_fence(syncobj, last_update);
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else
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drm_syncobj_add_point(syncobj, chain, last_update, point);
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}
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static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
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{
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struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
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@ -638,18 +708,23 @@ out:
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*
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* Update the bo_va directly after setting its address. Errors are not
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* vital here, so they are not reported back to userspace.
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*
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* Returns resulting fence if freed BO(s) got cleared from the PT.
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* otherwise stub fence in case of error.
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*/
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static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_bo_va *bo_va,
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uint32_t operation)
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static struct dma_fence *
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amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_bo_va *bo_va,
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uint32_t operation)
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{
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struct dma_fence *fence = dma_fence_get_stub();
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int r;
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if (!amdgpu_vm_ready(vm))
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return;
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return fence;
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r = amdgpu_vm_clear_freed(adev, vm, NULL);
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r = amdgpu_vm_clear_freed(adev, vm, &fence);
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if (r)
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goto error;
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@ -665,6 +740,8 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
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error:
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if (r && r != -ERESTARTSYS)
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DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
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return fence;
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}
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/**
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@ -713,6 +790,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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struct amdgpu_fpriv *fpriv = filp->driver_priv;
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struct amdgpu_bo *abo;
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struct amdgpu_bo_va *bo_va;
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struct drm_syncobj *timeline_syncobj = NULL;
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struct dma_fence_chain *timeline_chain = NULL;
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struct dma_fence *fence;
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struct drm_exec exec;
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uint64_t va_flags;
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uint64_t vm_size;
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@ -827,9 +907,24 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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default:
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break;
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}
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if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm)
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amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
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args->operation);
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if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) {
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r = amdgpu_gem_update_timeline_node(filp,
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args->vm_timeline_syncobj_out,
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args->vm_timeline_point,
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&timeline_syncobj,
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&timeline_chain);
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fence = amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
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args->operation);
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if (!r)
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amdgpu_gem_update_bo_mapping(filp, bo_va,
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args->operation,
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args->vm_timeline_point,
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fence, timeline_syncobj,
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timeline_chain);
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}
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error:
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drm_exec_fini(&exec);
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@ -857,6 +857,15 @@ struct drm_amdgpu_gem_va {
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__u64 offset_in_bo;
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/** Specify mapping size. Must be correctly aligned. */
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__u64 map_size;
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/**
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* vm_timeline_point is a sequence number used to add new timeline point.
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*/
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__u64 vm_timeline_point;
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/**
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* The vm page table update fence is installed in given vm_timeline_syncobj_out
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* at vm_timeline_point.
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*/
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__u32 vm_timeline_syncobj_out;
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};
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#define AMDGPU_HW_IP_GFX 0
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