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ACPICA: Align comments in TPRn-related structures
Align comments in ACPI_TPRN_BASE_REG and ACPI_TPRN_LIMIT_REG structures.
Link: 95815d5509
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/2286538.NgBsaNRSFp@rafael.j.wysocki
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1 changed files with 14 additions and 16 deletions
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@ -1998,14 +1998,10 @@ struct acpi_tpr_array {
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struct acpi_tpr_instance {
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u32 flags;
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u32 tpr_cnt;
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struct acpi_tpr_array tpr_array[];
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};
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struct acpi_tpr_aux_sr {
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u32 srl_cnt;
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/*
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* ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[];
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*/
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};
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/*
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@ -2022,13 +2018,14 @@ struct acpi_tprn_base_reg {
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u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */
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u64 enable:1; /* 0 == range enabled, 1 == range disabled */
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u64 reserved1:15;
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u64 tpr_base_rw:44; /*
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* Minimal TPRn_Base resolution is 1MB.
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* Applied to the incoming address, to determine if
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* an access fall within the TPRn defined region.
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* Width is determined by a bus width which can be
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* obtained via CPUID function 0x80000008.
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*/
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u64 tpr_base_rw:44;
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/*
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* Minimal TPRn_Base resolution is 1MB.
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* Applied to the incoming address, to determine if
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* an access fall within the TPRn defined region.
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* Width is determined by a bus width which can be
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* obtained via CPUID function 0x80000008.
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*/
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};
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/*
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@ -2045,11 +2042,12 @@ struct acpi_tprn_limit_reg {
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u64 rw:1; /* access: 1 == RO, 0 == RW (for TPR must be RW) */
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u64 enable:1; /* 0 == range enabled, 1 == range disabled */
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u64 reserved1:15;
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u64 tpr_limit_rw:44; /*
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* Minimal TPRn_Limit resolution is 1MB.
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* These bits define TPR limit address.
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* Width is determined by a bus width.
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*/
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u64 tpr_limit_rw:44;
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/*
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* Minimal TPRn_Limit resolution is 1MB.
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* These bits define TPR limit address.
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* Width is determined by a bus width.
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*/
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};
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/*
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