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firmware: qcom_scm: Rename peripheral as pas_id
Peripheral and pas_id refers to unique id for a subsystem and used only when peripheral authentication service from secure world is utilized. Lets rename peripheral to pas_id to reflect closer to its meaning. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260105-kvmrprocv10-v10-3-022e96815380@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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2 changed files with 20 additions and 20 deletions
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@ -562,7 +562,7 @@ static void qcom_scm_set_download_mode(u32 dload_mode)
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* qcom_scm_pas_init_image() - Initialize peripheral authentication service
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* state machine for a given peripheral, using the
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* metadata
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* @peripheral: peripheral id
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* @pas_id: peripheral authentication service id
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* @metadata: pointer to memory containing ELF header, program header table
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* and optional blob of data used for authenticating the metadata
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* and the rest of the firmware
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@ -575,7 +575,7 @@ static void qcom_scm_set_download_mode(u32 dload_mode)
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* track the metadata allocation, this needs to be released by invoking
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* qcom_scm_pas_metadata_release() by the caller.
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*/
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int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
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int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
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struct qcom_scm_pas_metadata *ctx)
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{
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dma_addr_t mdata_phys;
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@ -585,7 +585,7 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
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.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
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.args[0] = peripheral,
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.args[0] = pas_id,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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@ -656,20 +656,20 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release);
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/**
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* qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
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* for firmware loading
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* @peripheral: peripheral id
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* @pas_id: peripheral authentication service id
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* @addr: start address of memory area to prepare
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* @size: size of the memory area to prepare
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
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int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size)
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{
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
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.arginfo = QCOM_SCM_ARGS(3),
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.args[0] = peripheral,
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.args[0] = pas_id,
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.args[1] = addr,
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.args[2] = size,
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.owner = ARM_SMCCC_OWNER_SIP,
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@ -697,18 +697,18 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup);
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/**
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* qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
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* and reset the remote processor
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* @peripheral: peripheral id
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* @pas_id: peripheral authentication service id
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*
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* Return 0 on success.
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*/
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int qcom_scm_pas_auth_and_reset(u32 peripheral)
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int qcom_scm_pas_auth_and_reset(u32 pas_id)
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{
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
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.arginfo = QCOM_SCM_ARGS(1),
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.args[0] = peripheral,
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.args[0] = pas_id,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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@ -733,18 +733,18 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset);
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/**
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* qcom_scm_pas_shutdown() - Shut down the remote processor
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* @peripheral: peripheral id
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* @pas_id: peripheral authentication service id
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_shutdown(u32 peripheral)
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int qcom_scm_pas_shutdown(u32 pas_id)
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{
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
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.arginfo = QCOM_SCM_ARGS(1),
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.args[0] = peripheral,
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.args[0] = pas_id,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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@ -770,18 +770,18 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown);
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/**
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* qcom_scm_pas_supported() - Check if the peripheral authentication service is
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* available for the given peripherial
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* @peripheral: peripheral id
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* @pas_id: peripheral authentication service id
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*
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* Returns true if PAS is supported for this peripheral, otherwise false.
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*/
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bool qcom_scm_pas_supported(u32 peripheral)
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bool qcom_scm_pas_supported(u32 pas_id)
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{
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
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.arginfo = QCOM_SCM_ARGS(1),
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.args[0] = peripheral,
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.args[0] = pas_id,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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@ -72,13 +72,13 @@ struct qcom_scm_pas_metadata {
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ssize_t size;
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};
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int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
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int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
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struct qcom_scm_pas_metadata *ctx);
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void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
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int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
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int qcom_scm_pas_auth_and_reset(u32 peripheral);
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int qcom_scm_pas_shutdown(u32 peripheral);
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bool qcom_scm_pas_supported(u32 peripheral);
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int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size);
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int qcom_scm_pas_auth_and_reset(u32 pas_id);
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int qcom_scm_pas_shutdown(u32 pas_id);
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bool qcom_scm_pas_supported(u32 pas_id);
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int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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