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drm/i915/display: Add missing clock to C10 PHY state compute/HW readout
Clock value is missing from C10 hw readout stage. Let's fix this. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20251015125446.3931198-8-mika.kahola@intel.com
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2 changed files with 7 additions and 0 deletions
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@ -2103,6 +2103,9 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
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return 0;
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}
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static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
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const struct intel_c10pll_state *pll_state);
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static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
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struct intel_c10pll_state *pll_state)
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{
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@ -2127,6 +2130,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
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pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));
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intel_cx0_phy_transaction_end(encoder, wakeref);
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pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
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}
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static void intel_c10_pll_program(struct intel_display *display,
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@ -332,6 +332,8 @@ void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u6
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c10_curve_1, c10_curve_2, prescaler_divider,
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&pll_params);
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pll_state->clock = pixel_clock;
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pll_state->tx = 0x10;
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pll_state->cmn = 0x1;
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pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |
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