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drm/amdgpu/discovery: add vcn and jpeg ip block

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Add VCN and jpeg IPs v5_3_0 blocks.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Saleemkhan Jamadar 2025-10-05 14:27:52 +05:30 • committed by Alex Deucher
parent 4aeaf3cbfa
commit 637fd8dedf
3 changed files with 44 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
View file

@ -112,6 +112,8 @@
#include "vcn_v5_0_1.h"
#include "jpeg_v5_0_0.h"
#include "jpeg_v5_0_1.h"
#include "jpeg_v5_3_0.h"
#include "amdgpu_ras_mgr.h"
#include "amdgpu_vpe.h"
@ -2538,6 +2540,10 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
break;
case IP_VERSION(5, 3, 0):
amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block);
break;
case IP_VERSION(5, 0, 1):
amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block);

2
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View file

@ -63,6 +63,7 @@
#define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin"
#define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin"
#define FIRMWARE_VCN5_0_1 "amdgpu/vcn_5_0_1.bin"
#define FIRMWARE_VCN5_3_0 "amdgpu/vcn_5_3_0.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN);
MODULE_FIRMWARE(FIRMWARE_PICASSO);
@ -90,6 +91,7 @@ MODULE_FIRMWARE(FIRMWARE_VCN4_0_6);
MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1);
MODULE_FIRMWARE(FIRMWARE_VCN5_0_0);
MODULE_FIRMWARE(FIRMWARE_VCN5_0_1);
MODULE_FIRMWARE(FIRMWARE_VCN5_3_0);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev);

39
drivers/gpu/drm/amd/amdgpu/soc21.c
View file

@ -141,6 +141,31 @@ static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
.codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
};
static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = {
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
};
static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = {
.codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0),
.codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0,
};
static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = {
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
};
static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = {
.codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0),
.codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0,
};
static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
const struct amdgpu_video_codecs **codecs)
{
@ -185,6 +210,12 @@ static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
else
*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
return 0;
case IP_VERSION(5, 3, 0):
if (encode)
*codecs = &vcn_5_3_0_video_codecs_encode_vcn0;
else
*codecs = &vcn_5_3_0_video_codecs_decode_vcn0;
return 0;
default:
return -EINVAL;
}
@ -800,9 +831,11 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
adev->external_rev_id = adev->rev_id + 0x50;
break;
case IP_VERSION(11, 5, 4):
adev->cg_flags = 0;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x1;
adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x1;
break;
default:
/* FIXME: not supported yet */