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Renesas RZ/N2H DT Binding Definitions

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DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087)
 SoC, shared by driver and DT source files.
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Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17

Renesas RZ/N2H DT Binding Definitions

DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087)
SoC, shared by driver and DT source files.
This commit is contained in:
Geert Uytterhoeven 2025-06-19 20:19:13 +02:00
commit 5701451e84
3 changed files with 42 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

5
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
View file

@ -53,6 +53,7 @@ properties:
- renesas,r8a779g0-cpg-mssr # R-Car V4H
- renesas,r8a779h0-cpg-mssr # R-Car V4M
- renesas,r9a09g077-cpg-mssr # RZ/T2H
- renesas,r9a09g087-cpg-mssr # RZ/N2H
reg:
minItems: 1
@ -112,7 +113,9 @@ allOf:
properties:
compatible:
contains:
const: renesas,r9a09g077-cpg-mssr
enum:
- renesas,r9a09g077-cpg-mssr
- renesas,r9a09g087-cpg-mssr
then:
properties:
reg:

10
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
View file

@ -602,6 +602,16 @@ properties:
- renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
- const: renesas,r9a09g077
- description: RZ/N2H (R9A09G087)
items:
- enum:
- renesas,rzn2h-evk # RZ/N2H Evaluation Board (RTK9RZN2H0S00000BJ)
- enum:
- renesas,r9a09g087m04 # RZ/N2H with Single Cortex-A55 + Dual Cortex-R52 - no security
- renesas,r9a09g087m24 # RZ/N2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
- renesas,r9a09g087m44 # RZ/N2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
- const: renesas,r9a09g087
additionalProperties: true
...

28
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h Normal file
View file

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A09G087 CPG Core Clocks */
#define R9A09G087_CLK_CA55C0 0
#define R9A09G087_CLK_CA55C1 1
#define R9A09G087_CLK_CA55C2 2
#define R9A09G087_CLK_CA55C3 3
#define R9A09G087_CLK_CA55S 4
#define R9A09G087_CLK_CR52_CPU0 5
#define R9A09G087_CLK_CR52_CPU1 6
#define R9A09G087_CLK_CKIO 7
#define R9A09G087_CLK_PCLKAH 8
#define R9A09G087_CLK_PCLKAM 9
#define R9A09G087_CLK_PCLKAL 10
#define R9A09G087_CLK_PCLKGPTL 11
#define R9A09G087_CLK_PCLKH 12
#define R9A09G087_CLK_PCLKM 13
#define R9A09G087_CLK_PCLKL 14
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */