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clk: renesas: Add missing log message terminators

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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Link: https://patch.msgid.link/cd0b3624066b80ed0bb00d489c99e2c1a06d755f.1768480559.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2026-01-15 13:36:56 +01:00
parent 5a4326f2e3
commit 4fef3fd633
4 changed files with 9 additions and 9 deletions
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4
drivers/clk/renesas/clk-vbattb.c
View file

@ -69,11 +69,11 @@ static void vbattb_clk_action(void *data)
ret = reset_control_assert(rstc);
if (ret)
dev_err(dev, "Failed to de-assert reset!");
dev_err(dev, "Failed to de-assert reset!\n");
ret = pm_runtime_put_sync(dev);
if (ret < 0)
dev_err(dev, "Failed to runtime suspend!");
dev_err(dev, "Failed to runtime suspend!\n");
of_clk_del_provider(dev->of_node);
}

2
drivers/clk/renesas/renesas-cpg-mssr.c
View file

@ -404,7 +404,7 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
}
if (IS_ERR(clk))
dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
dev_err(dev, "Cannot get %s clock %u: %ld\n", type, clkidx,
PTR_ERR(clk));
else
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",

6
drivers/clk/renesas/rzg2l-cpg.c
View file

@ -979,7 +979,7 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
!(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
if (ret) {
dev_err(priv->dev, "failed to release pll5 lock");
dev_err(priv->dev, "failed to release pll5 lock\n");
return ret;
}
@ -1006,7 +1006,7 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
if (ret) {
dev_err(priv->dev, "failed to lock pll5");
dev_err(priv->dev, "failed to lock pll5\n");
return ret;
}
@ -1214,7 +1214,7 @@ static struct clk
}
if (IS_ERR(clk))
dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
dev_err(dev, "Cannot get %s clock %u: %ld\n", type, clkidx,
PTR_ERR(clk));
else
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",

6
drivers/clk/renesas/rzv2h-cpg.c
View file

@ -602,7 +602,7 @@ static int rzv2h_cpg_pll_set_rate(struct pll_clk *pll_clk,
val, !(val & CPG_PLL_MON_LOCK),
100, 2000);
if (ret) {
dev_err(priv->dev, "Failed to put PLLDSI into standby mode");
dev_err(priv->dev, "Failed to put PLLDSI into standby mode\n");
return ret;
}
@ -630,7 +630,7 @@ static int rzv2h_cpg_pll_set_rate(struct pll_clk *pll_clk,
val, (val & CPG_PLL_MON_LOCK),
100, 2000);
if (ret) {
dev_err(priv->dev, "Failed to put PLLDSI into normal mode");
dev_err(priv->dev, "Failed to put PLLDSI into normal mode\n");
return ret;
}
@ -1013,7 +1013,7 @@ static struct clk
}
if (IS_ERR(clk))
dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
dev_err(dev, "Cannot get %s clock %u: %ld\n", type, clkidx,
PTR_ERR(clk));
else
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",