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ASoC: sophgo: add CV1800B internal ADC codec driver
Codec DAI endpoint for RXADC + basic controls. THe codec have basic volume control. Which is imlemented by lookup table for simplicity. The codec expects set_sysclk callback to adjust internal mclk divider. Signed-off-by: Anton D. Stavinskii <stavinsky@gmail.com> Link: https://patch.msgid.link/20260120-cv1800b-i2s-driver-v4-4-6ef787dc6426@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Anton D. Stavinskii
Mark Brown
parent
c294aafe47
commit
4cf8752a03
3 changed files with 335 additions and 0 deletions
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@ -22,4 +22,16 @@ config SND_SOC_CV1800B_TDM
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To compile the driver as a module, choose M here: the module will
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be called cv1800b_tdm.
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config SND_SOC_CV1800B_ADC_CODEC
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tristate "Sophgo CV1800B/SG2002 internal ADC codec"
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depends on SND_SOC
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help
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This driver provides an ASoC codec DAI for capture and basic
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control of the RXADC registers.
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Say Y or M to build support for the Sophgo CV1800B
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internal analog ADC codec block (RXADC).
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The module will be called cv1800b-sound-adc
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endmenu
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@ -1,3 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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# Sophgo Platform Support
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obj-$(CONFIG_SND_SOC_CV1800B_TDM) += cv1800b-tdm.o
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obj-$(CONFIG_SND_SOC_CV1800B_ADC_CODEC) += cv1800b-sound-adc.o
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322
sound/soc/sophgo/cv1800b-sound-adc.c
Normal file
322
sound/soc/sophgo/cv1800b-sound-adc.c
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@ -0,0 +1,322 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Internal adc codec for cv1800b compatible SoC
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*
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <sound/soc.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <sound/tlv.h>
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#include <sound/soc-component.h>
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#include <sound/control.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#define CV1800B_RXADC_WORD_LEN 16
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#define CV1800B_RXADC_CHANNELS 2
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#define CV1800B_RXADC_CTRL0 0x00
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#define CV1800B_RXADCC_CTRL1 0x04
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#define CV1800B_RXADC_STATUS 0x08
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#define CV1800B_RXADC_CLK 0x0c
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#define CV1800B_RXADC_ANA0 0x10
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#define CV1800B_RXADC_ANA1 0x14
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#define CV1800B_RXADC_ANA2 0x18
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#define CV1800B_RXADC_ANA3 0x1c
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#define CV1800B_RXADC_ANA4 0x20
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/* CV1800B_RXADC_CTRL0 */
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#define REG_RXADC_EN GENMASK(0, 0)
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#define REG_I2S_TX_EN GENMASK(1, 1)
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/* CV1800B_RXADCC_CTRL1 */
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#define REG_RXADC_CIC_OPT GENMASK(1, 0)
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#define REG_RXADC_IGR_INIT GENMASK(8, 8)
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/* CV1800B_RXADC_ANA0 */
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#define REG_GSTEPL_RXPGA GENMASK(12, 0)
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#define REG_G6DBL_RXPGA GENMASK(13, 13)
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#define REG_GAINL_RXADC GENMASK(15, 14)
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#define REG_GSTEPR_RXPGA GENMASK(28, 16)
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#define REG_G6DBR_RXPGA GENMASK(29, 29)
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#define REG_GAINR_RXADC GENMASK(31, 30)
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#define REG_COMB_LEFT_VOLUME GENMASK(15, 0)
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#define REG_COMB_RIGHT_VOLUME GENMASK(31, 16)
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/* CV1800B_RXADC_ANA2 */
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#define REG_MUTEL_RXPGA GENMASK(0, 0)
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#define REG_MUTER_RXPGA GENMASK(1, 1)
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/* CV1800B_RXADC_CLK */
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#define REG_RXADC_CLK_INV GENMASK(0, 0)
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#define REG_RXADC_SCK_DIV GENMASK(15, 8)
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#define REG_RXADC_DLYEN GENMASK(23, 16)
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enum decimation_values {
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DECIMATION_64 = 0,
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DECIMATION_128,
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DECIMATION_256,
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DECIMATION_512,
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};
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static const u32 cv1800b_gains[] = {
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0x0001, /* 0dB */
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0x0002, /* 2dB */
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0x0004, /* 4dB */
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0x0008, /* 6dB */
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0x0010, /* 8dB */
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0x0020, /* 10dB */
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0x0040, /* 12dB */
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0x0080, /* 14dB */
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0x0100, /* 16dB */
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0x0200, /* 18dB */
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0x0400, /* 20dB */
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0x0800, /* 22dB */
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0x1000, /* 24dB */
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0x2400, /* 26dB */
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0x2800, /* 28dB */
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0x3000, /* 30dB */
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0x6400, /* 32dB */
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0x6800, /* 34dB */
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0x7000, /* 36dB */
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0xA400, /* 38dB */
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0xA800, /* 40dB */
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0xB000, /* 42dB */
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0xE400, /* 44dB */
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0xE800, /* 46dB */
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0xF000, /* 48dB */
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};
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struct cv1800b_priv {
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void __iomem *regs;
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struct device *dev;
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unsigned int mclk_rate;
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};
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static int cv1800b_adc_setbclk_div(struct cv1800b_priv *priv, unsigned int rate)
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{
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u32 val;
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u32 bclk_div;
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u64 tmp;
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if (!priv->mclk_rate || !rate)
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return -EINVAL;
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tmp = priv->mclk_rate;
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tmp /= CV1800B_RXADC_WORD_LEN;
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tmp /= CV1800B_RXADC_CHANNELS;
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tmp /= rate;
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tmp /= 2;
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if (!tmp) {
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dev_err(priv->dev, "computed BCLK divider is zero\n");
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return -EINVAL;
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}
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if (tmp > 256) {
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dev_err(priv->dev, "BCLK divider %llu out of range\n", tmp);
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return -EINVAL;
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}
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bclk_div = tmp - 1;
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val = readl(priv->regs + CV1800B_RXADC_CLK);
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val = u32_replace_bits(val, bclk_div, REG_RXADC_SCK_DIV);
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/* Vendor value for 48kHz, tested on SG2000/SG2002 */
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val = u32_replace_bits(val, 0x19, REG_RXADC_DLYEN);
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writel(val, priv->regs + CV1800B_RXADC_CLK);
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return 0;
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}
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static void cv1800b_adc_enable(struct cv1800b_priv *priv, bool enable)
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{
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u32 val;
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val = readl(priv->regs + CV1800B_RXADC_CTRL0);
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val = u32_replace_bits(val, enable, REG_RXADC_EN);
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val = u32_replace_bits(val, enable, REG_I2S_TX_EN);
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writel(val, priv->regs + CV1800B_RXADC_CTRL0);
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}
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static unsigned int cv1800b_adc_calc_db(u32 ana0, bool right)
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{
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u32 step_mask = right ? FIELD_GET(REG_GSTEPR_RXPGA, ana0) :
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FIELD_GET(REG_GSTEPL_RXPGA, ana0);
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u32 coarse = right ? FIELD_GET(REG_GAINR_RXADC, ana0) :
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FIELD_GET(REG_GAINL_RXADC, ana0);
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bool g6db = right ? FIELD_GET(REG_G6DBR_RXPGA, ana0) :
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FIELD_GET(REG_G6DBL_RXPGA, ana0);
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u32 step = step_mask ? __ffs(step_mask) : 0;
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step = min(step, 12U);
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coarse = min(coarse, 3U);
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return 2 * step + 6 * coarse + (g6db ? 6 : 0);
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}
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static int cv1800b_adc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct cv1800b_priv *priv = snd_soc_dai_get_drvdata(dai);
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unsigned int rate = params_rate(params);
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u32 val;
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int ret;
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ret = cv1800b_adc_setbclk_div(priv, rate);
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if (ret) {
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dev_err(priv->dev,
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"could not set rate, check DT node for fixed clock\n");
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return ret;
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}
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/* init adc */
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val = readl(priv->regs + CV1800B_RXADCC_CTRL1);
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val = u32_replace_bits(val, 1, REG_RXADC_IGR_INIT);
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val = u32_replace_bits(val, DECIMATION_64, REG_RXADC_CIC_OPT);
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writel(val, priv->regs + CV1800B_RXADCC_CTRL1);
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return 0;
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}
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static int cv1800b_adc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct cv1800b_priv *priv = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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cv1800b_adc_enable(priv, true);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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cv1800b_adc_enable(priv, false);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int cv1800b_adc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct cv1800b_priv *priv = snd_soc_dai_get_drvdata(dai);
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priv->mclk_rate = freq;
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dev_dbg(priv->dev, "mclk is set to %u\n", freq);
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return 0;
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}
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static const struct snd_soc_dai_ops cv1800b_adc_dai_ops = {
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.hw_params = cv1800b_adc_hw_params,
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.set_sysclk = cv1800b_adc_dai_set_sysclk,
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.trigger = cv1800b_adc_dai_trigger,
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};
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static struct snd_soc_dai_driver cv1800b_adc_dai = {
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.name = "adc-hifi",
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.capture = { .stream_name = "ADC Capture",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE },
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.ops = &cv1800b_adc_dai_ops,
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};
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static int cv1800b_adc_volume_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct cv1800b_priv *priv = snd_soc_component_get_drvdata(component);
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u32 ana0 = readl(priv->regs + CV1800B_RXADC_ANA0);
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unsigned int left = cv1800b_adc_calc_db(ana0, false);
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unsigned int right = cv1800b_adc_calc_db(ana0, true);
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ucontrol->value.integer.value[0] = min(left / 2, 24U);
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ucontrol->value.integer.value[1] = min(right / 2, 24U);
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return 0;
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}
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static int cv1800b_adc_volume_set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct cv1800b_priv *priv = snd_soc_component_get_drvdata(component);
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u32 v_left = clamp_t(u32, ucontrol->value.integer.value[0], 0, 24);
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u32 v_right = clamp_t(u32, ucontrol->value.integer.value[1], 0, 24);
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u32 val;
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val = readl(priv->regs + CV1800B_RXADC_ANA0);
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val = u32_replace_bits(val, cv1800b_gains[v_left],
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REG_COMB_LEFT_VOLUME);
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val = u32_replace_bits(val, cv1800b_gains[v_right],
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REG_COMB_RIGHT_VOLUME);
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writel(val, priv->regs + CV1800B_RXADC_ANA0);
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return 0;
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}
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static DECLARE_TLV_DB_SCALE(cv1800b_volume_tlv, 0, 200, 0);
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static const struct snd_kcontrol_new cv1800b_adc_controls[] = {
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SOC_DOUBLE_EXT_TLV("Internal I2S Capture Volume", SND_SOC_NOPM, 0, 16, 24, false,
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cv1800b_adc_volume_get, cv1800b_adc_volume_set,
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cv1800b_volume_tlv),
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};
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static const struct snd_soc_component_driver cv1800b_adc_component = {
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.name = "cv1800b-adc-codec",
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.controls = cv1800b_adc_controls,
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.num_controls = ARRAY_SIZE(cv1800b_adc_controls),
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};
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static int cv1800b_adc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct cv1800b_priv *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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priv->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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platform_set_drvdata(pdev, priv);
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return devm_snd_soc_register_component(&pdev->dev,
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&cv1800b_adc_component,
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&cv1800b_adc_dai, 1);
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}
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static const struct of_device_id cv1800b_adc_of_match[] = {
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{ .compatible = "sophgo,cv1800b-sound-adc" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, cv1800b_adc_of_match);
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static struct platform_driver cv1800b_adc_driver = {
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.probe = cv1800b_adc_probe,
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.driver = {
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.name = "cv1800b-sound-adc",
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.of_match_table = cv1800b_adc_of_match,
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},
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};
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module_platform_driver(cv1800b_adc_driver);
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MODULE_DESCRIPTION("ADC codec for CV1800B");
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MODULE_AUTHOR("Anton D. Stavinskii <stavinsky@gmail.com>");
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MODULE_LICENSE("GPL");
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