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dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller
Add bindings for STM32 Octo Memory Manager (OMM) controller.
OMM manages:
- the muxing between 2 OSPI busses and 2 output ports.
There are 4 possible muxing configurations:
- direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
output is on port 2
- OSPI1 and OSPI2 are multiplexed over the same output port 1
- swapped mode (no multiplexing), OSPI1 output is on port 2,
OSPI2 output is on port 1
- OSPI1 and OSPI2 are multiplexed over the same output port 2
- the split of the memory area shared between the 2 OSPI instances.
- chip select selection override.
- the time between 2 transactions in multiplexed mode.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250428-upstream_ospi_v6-v11-1-1548736fd9d2@foss.st.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Patrice Chotard
Krzysztof Kozlowski
parent
66db876162
commit
4a98ec836a
1 changed files with 226 additions and 0 deletions
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32 Octo Memory Manager (OMM)
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maintainers:
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- Patrice Chotard <patrice.chotard@foss.st.com>
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description: |
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The STM32 Octo Memory Manager is a low-level interface that enables an
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efficient OCTOSPI pin assignment with a full I/O matrix (before alternate
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function map) and multiplex of single/dual/quad/octal SPI interfaces over
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the same bus. It Supports up to:
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- Two single/dual/quad/octal SPI interfaces
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- Two ports for pin assignment
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properties:
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compatible:
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const: st,stm32mp25-omm
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"#address-cells":
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const: 2
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"#size-cells":
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const: 1
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ranges:
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description: |
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Reflects the memory layout per OSPI instance.
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Format:
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<chip-select> 0 <registers base address> <size>
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minItems: 2
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maxItems: 2
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reg:
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items:
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- description: OMM registers
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- description: OMM memory map area
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reg-names:
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items:
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- const: regs
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- const: memory_map
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memory-region:
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description:
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Memory region shared between the 2 OCTOSPI instance.
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One or two phandle to a node describing a memory mapped region
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depending of child number.
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minItems: 1
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maxItems: 2
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memory-region-names:
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description:
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Identify to which OSPI instance the memory region belongs to.
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items:
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enum: [ospi1, ospi2]
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minItems: 1
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maxItems: 2
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: omm
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- const: ospi1
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- const: ospi2
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resets:
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maxItems: 3
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reset-names:
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items:
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- const: omm
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- const: ospi1
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- const: ospi2
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access-controllers:
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maxItems: 1
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power-domains:
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maxItems: 1
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st,syscfg-amcr:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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The Address Mapping Control Register (AMCR) is used to split the 256MB
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memory map area shared between the 2 OSPI instance. The Octo Memory
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Manager sets the AMCR depending of the memory-region configuration.
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The memory split bitmask description is:
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- 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped
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- 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes)
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- 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes)
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- 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes)
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- 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes)
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items:
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- items:
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- description: phandle to syscfg
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- description: register offset within syscfg
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- description: register bitmask for memory split
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st,omm-req2ack-ns:
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description:
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In multiplexed mode (MUXEN = 1), this field defines the time in
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nanoseconds between two transactions.
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default: 0
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st,omm-cssel-ovr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Configure the chip select selector override for the 2 OCTOSPIs.
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- 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1
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- 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS1
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- 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS2
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- 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS2
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minimum: 0
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maximum: 3
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default: 0
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st,omm-mux:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Configure the muxing between the 2 OCTOSPIs busses and the 2 output ports.
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- 0: direct mode
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- 1: mux OCTOSPI1 and OCTOSPI2 to port 1
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- 2: swapped mode
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- 3: mux OCTOSPI1 and OCTOSPI2 to port 2
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minimum: 0
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maximum: 3
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default: 0
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patternProperties:
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^spi@[0-9]:
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type: object
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$ref: /schemas/spi/st,stm32mp25-ospi.yaml#
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description: Required spi child node
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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- st,syscfg-amcr
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/st,stm32mp25-rcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/st,stm32mp25-rcc.h>
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ommanager@40500000 {
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compatible = "st,stm32mp25-omm";
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reg = <0x40500000 0x400>, <0x60000000 0x10000000>;
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reg-names = "regs", "memory_map";
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ranges = <0 0 0x40430000 0x400>,
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<1 0 0x40440000 0x400>;
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memory-region = <&mm_ospi1>, <&mm_ospi2>;
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memory-region-names = "ospi1", "ospi2";
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pinctrl-0 = <&ospi_port1_clk_pins_a
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&ospi_port1_io03_pins_a
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&ospi_port1_cs0_pins_a>;
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pinctrl-1 = <&ospi_port1_clk_sleep_pins_a
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&ospi_port1_io03_sleep_pins_a
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&ospi_port1_cs0_sleep_pins_a>;
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pinctrl-names = "default", "sleep";
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clocks = <&rcc CK_BUS_OSPIIOM>,
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<&scmi_clk CK_SCMI_OSPI1>,
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<&scmi_clk CK_SCMI_OSPI2>;
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clock-names = "omm", "ospi1", "ospi2";
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resets = <&rcc OSPIIOM_R>,
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<&scmi_reset RST_SCMI_OSPI1>,
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<&scmi_reset RST_SCMI_OSPI2>;
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reset-names = "omm", "ospi1", "ospi2";
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access-controllers = <&rifsc 111>;
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power-domains = <&CLUSTER_PD>;
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#address-cells = <2>;
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#size-cells = <1>;
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st,syscfg-amcr = <&syscfg 0x2c00 0x7>;
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st,omm-req2ack-ns = <0>;
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st,omm-mux = <0>;
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st,omm-cssel-ovr = <0>;
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spi@0 {
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compatible = "st,stm32mp25-ospi";
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reg = <0 0 0x400>;
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memory-region = <&mm_ospi1>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&hpdma 2 0x62 0x00003121 0x0>,
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<&hpdma 2 0x42 0x00003112 0x0>;
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dma-names = "tx", "rx";
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clocks = <&scmi_clk CK_SCMI_OSPI1>;
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resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>;
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access-controllers = <&rifsc 74>;
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power-domains = <&CLUSTER_PD>;
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#address-cells = <1>;
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#size-cells = <0>;
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st,syscfg-dlyb = <&syscfg 0x1000>;
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};
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spi@1 {
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compatible = "st,stm32mp25-ospi";
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reg = <1 0 0x400>;
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memory-region = <&mm_ospi1>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&hpdma 3 0x62 0x00003121 0x0>,
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<&hpdma 3 0x42 0x00003112 0x0>;
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dma-names = "tx", "rx";
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clocks = <&scmi_clk CK_KER_OSPI2>;
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resets = <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSPI1DLL>;
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access-controllers = <&rifsc 75>;
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power-domains = <&CLUSTER_PD>;
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#address-cells = <1>;
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#size-cells = <0>;
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st,syscfg-dlyb = <&syscfg 0x1000>;
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};
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};
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