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serial: sh-sci: Add support for RZ/G3E RSCI
Add support for RZ/G3E RSCI. RSCI IP found on the RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. It has 6 clocks(5 module clocks + 1 external clock) instead of 3 clocks(2 module clocks + 1 external clock) on T2H, has 6 irqs compared to 4 on RZ/T2H and has multiple resets. Add support for the hardware flow control. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20251129164325.209213-18-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Biju Das
Greg Kroah-Hartman
parent
068b862f50
commit
42eeed6d9f
3 changed files with 257 additions and 9 deletions
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@ -11,6 +11,8 @@
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#include <linux/serial_core.h>
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#include <linux/serial_sci.h>
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#include <linux/tty_flip.h>
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#include "serial_mctrl_gpio.h"
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#include "rsci.h"
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MODULE_IMPORT_NS("SH_SCI");
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@ -59,6 +61,41 @@ MODULE_IMPORT_NS("SH_SCI");
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#define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */
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#define CCR1_CTSE BIT(0) /* CTS Enable */
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/* CCR2 (Common Control Register 2) */
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#define CCR2_INIT 0xFF000004
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#define CCR2_CKS_TCLK (0) /* TCLK clock */
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#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */
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#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */
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#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */
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#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */
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#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */
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#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */
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#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */
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/* CCR3 (Common Control Register 3) */
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#define CCR3_INIT 0x1203
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#define CCR3_BLK BIT(29) /* Block Transfer Mode */
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#define CCR3_GM BIT(28) /* GSM Mode */
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#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */
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#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */
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#define CCR3_DEN BIT(21) /* Driver Enabled */
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#define CCR3_FM BIT(20) /* FIFO Mode Select */
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#define CCR3_MP BIT(19) /* Multi-Processor Mode */
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#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */
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#define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */
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#define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */
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#define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */
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#define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */
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#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */
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#define CCR3_STP BIT(14) /* Stop bit Length */
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#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */
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#define CCR3_LSBF BIT(12) /* LSB First select */
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#define CCR3_CHR1 BIT(9) /* Character Length */
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#define CCR3_CHR0 BIT(8) /* Character Length */
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#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */
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#define CCR3_CPOL BIT(1) /* Clock Polarity Select */
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#define CCR3_CPHA BIT(0) /* Clock Phase Select */
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/* FCR (FIFO Control Register) */
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#define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */
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#define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */
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@ -138,6 +175,29 @@ static void rsci_start_rx(struct uart_port *port)
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rsci_serial_out(port, CCR0, ctrl);
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}
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static void rsci_enable_ms(struct uart_port *port)
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{
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mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
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}
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static void rsci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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struct sci_port *s = to_sci_port(port);
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/* Use port-specific handler if provided */
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if (s->cfg->ops && s->cfg->ops->init_pins) {
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s->cfg->ops->init_pins(port, cflag);
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return;
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}
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if (!s->has_rtscts)
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return;
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if (s->autorts)
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rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) |
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CCR1_CTSE | CCR1_CTSPEN);
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}
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static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig)
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{
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u32 fcr = rsci_serial_in(port, FCR);
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@ -157,18 +217,119 @@ static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig)
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static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
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const struct ktermios *old)
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{
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unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT;
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unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0;
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unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
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struct sci_port *s = to_sci_port(port);
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unsigned int brr = 255, cks = 0;
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int min_err = INT_MAX, err;
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unsigned long max_freq = 0;
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unsigned int baud, i;
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unsigned long flags;
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unsigned int ctrl;
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int best_clk = -1;
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if ((termios->c_cflag & CSIZE) == CS7) {
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ccr3_val |= CCR3_CHR0;
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} else {
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termios->c_cflag &= ~CSIZE;
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termios->c_cflag |= CS8;
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}
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if (termios->c_cflag & PARENB)
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ccr1_val |= CCR1_PE;
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if (termios->c_cflag & PARODD)
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ccr1_val |= (CCR1_PE | CCR1_PM);
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if (termios->c_cflag & CSTOPB)
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ccr3_val |= CCR3_STP;
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/* Enable noise filter function */
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ccr1_val |= CCR1_NFEN;
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/*
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* earlyprintk comes here early on with port->uartclk set to zero.
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* the clock framework is not up and running at this point so here
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* we assume that 115200 is the maximum baud rate. please note that
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* the baud rate is not programmed during earlyprintk - it is assumed
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* that the previous boot loader has enabled required clocks and
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* setup the baud rate generator hardware for us already.
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*/
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if (!port->uartclk) {
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max_freq = 115200;
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} else {
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for (i = 0; i < SCI_NUM_CLKS; i++)
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max_freq = max(max_freq, s->clk_rates[i]);
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max_freq /= min_sr(s);
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}
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baud = uart_get_baud_rate(port, termios, old, 0, max_freq);
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if (!baud)
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goto done;
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/* Divided Functional Clock using standard Bit Rate Register */
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err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
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if (abs(err) < abs(min_err)) {
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best_clk = SCI_FCK;
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ccr0_val = 0;
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min_err = err;
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brr = brr1;
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cks = cks1;
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}
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done:
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if (best_clk >= 0)
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dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
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s->clks[best_clk], baud, min_err);
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sci_port_enable(s);
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uart_port_lock_irqsave(port, &flags);
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/* For now, only RX enabling is supported */
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if (termios->c_cflag & CREAD)
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uart_update_timeout(port, termios->c_cflag, baud);
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rsci_serial_out(port, CCR0, ccr0_val);
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ccr3_val |= CCR3_FM;
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rsci_serial_out(port, CCR3, ccr3_val);
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ccr2_val |= (cks << 20) | (brr << 8);
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rsci_serial_out(port, CCR2, ccr2_val);
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rsci_serial_out(port, CCR1, ccr1_val);
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rsci_serial_out(port, CCR4, ccr4_val);
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ctrl = rsci_serial_in(port, FCR);
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ctrl |= (FCR_RFRST | FCR_TFRST);
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rsci_serial_out(port, FCR, ctrl);
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if (s->rx_trigger > 1)
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rsci_scif_set_rtrg(port, s->rx_trigger);
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port->status &= ~UPSTAT_AUTOCTS;
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s->autorts = false;
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if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) {
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port->status |= UPSTAT_AUTOCTS;
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s->autorts = true;
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}
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rsci_init_pins(port, termios->c_cflag);
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rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
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rsci_serial_out(port, FFCLR, FFCLR_DRC);
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ccr0_val |= CCR0_RE;
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rsci_serial_out(port, CCR0, ccr0_val);
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if ((termios->c_cflag & CREAD) != 0)
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rsci_start_rx(port);
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uart_port_unlock_irqrestore(port, flags);
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sci_port_disable(s);
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if (UART_ENABLE_MS(port, termios->c_cflag))
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rsci_enable_ms(port);
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}
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static int rsci_txfill(struct uart_port *port)
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@ -193,13 +354,34 @@ static unsigned int rsci_tx_empty(struct uart_port *port)
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static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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/* Not supported yet */
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if (mctrl & TIOCM_LOOP) {
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/* Standard loopback mode */
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rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
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}
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}
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static unsigned int rsci_get_mctrl(struct uart_port *port)
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{
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/* Not supported yet */
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return 0;
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struct sci_port *s = to_sci_port(port);
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struct mctrl_gpios *gpios = s->gpios;
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unsigned int mctrl = 0;
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mctrl_gpio_get(gpios, &mctrl);
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/*
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* CTS/RTS is handled in hardware when supported, while nothing
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* else is wired up.
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*/
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if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))
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mctrl |= TIOCM_CTS;
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if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
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mctrl |= TIOCM_DSR;
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if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
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mctrl |= TIOCM_CAR;
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return mctrl;
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}
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static void rsci_clear_CFC(struct uart_port *port, unsigned int mask)
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@ -329,7 +511,8 @@ static void rsci_receive_chars(struct uart_port *port)
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continue;
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}
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/* Store data and status.
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/*
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* Store data and status.
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* Non FIFO mode is not supported
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*/
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if (rdat & RDR_FFER) {
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@ -363,6 +546,28 @@ static void rsci_receive_chars(struct uart_port *port)
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}
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}
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static void rsci_break_ctl(struct uart_port *port, int break_state)
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{
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unsigned short ccr0_val, ccr1_val;
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unsigned long flags;
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uart_port_lock_irqsave(port, &flags);
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ccr1_val = rsci_serial_in(port, CCR1);
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ccr0_val = rsci_serial_in(port, CCR0);
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if (break_state == -1) {
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ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT;
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ccr0_val &= ~CCR0_TE;
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} else {
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ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO;
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ccr0_val |= CCR0_TE;
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}
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rsci_serial_out(port, CCR1, ccr1_val);
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rsci_serial_out(port, CCR0, ccr0_val);
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uart_port_unlock_irqrestore(port, flags);
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}
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static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
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{
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u32 status;
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@ -384,12 +589,21 @@ done:
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static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl)
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{
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struct sci_port *s = to_sci_port(port);
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u32 ctrl_temp =
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s->params->param_bits->rxtx_enable | CCR0_TIE |
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s->hscif_tot;
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u32 ctrl_temp = s->params->param_bits->rxtx_enable;
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if (s->type == RSCI_PORT_SCIF16)
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ctrl_temp |= CCR0_TIE | s->hscif_tot;
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rsci_serial_out(port, CCR0, ctrl_temp);
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}
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static void rsci_finish_console_write(struct uart_port *port, u32 ctrl)
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{
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/* First set TE = 0 and then restore the CCR0 value */
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rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE);
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rsci_serial_out(port, CCR0, ctrl);
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}
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static const char *rsci_type(struct uart_port *port)
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{
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return "rsci";
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@ -419,6 +633,17 @@ static const struct sci_port_params_bits rsci_port_param_bits = {
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.poll_sent_bits = CSR_TDRE | CSR_TEND,
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};
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static const struct sci_port_params rsci_rzg3e_port_params = {
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.fifosize = 32,
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.overrun_reg = CSR,
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.overrun_mask = CSR_ORER,
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.sampling_rate_mask = SCI_SR(32),
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.error_mask = RSCI_DEFAULT_ERROR_MASK,
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.error_clear = RSCI_ERROR_CLEAR,
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.param_bits = &rsci_port_param_bits,
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.common_regs = &rsci_common_regs,
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};
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static const struct sci_port_params rsci_rzt2h_port_params = {
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.fifosize = 16,
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.overrun_reg = CSR,
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@ -437,6 +662,8 @@ static const struct uart_ops rsci_uart_ops = {
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.start_tx = rsci_start_tx,
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.stop_tx = rsci_stop_tx,
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.stop_rx = rsci_stop_rx,
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.enable_ms = rsci_enable_ms,
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.break_ctl = rsci_break_ctl,
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.startup = sci_startup,
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.shutdown = sci_shutdown,
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.set_termios = rsci_set_termios,
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@ -456,11 +683,19 @@ static const struct sci_port_ops rsci_port_ops = {
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.receive_chars = rsci_receive_chars,
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.poll_put_char = rsci_poll_put_char,
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.prepare_console_write = rsci_prepare_console_write,
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.finish_console_write = rsci_finish_console_write,
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.suspend_regs_size = rsci_suspend_regs_size,
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.set_rtrg = rsci_scif_set_rtrg,
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.shutdown_complete = rsci_shutdown_complete,
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};
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struct sci_of_data of_rsci_rzg3e_data = {
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.type = RSCI_PORT_SCIF32,
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.ops = &rsci_port_ops,
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.uart_ops = &rsci_uart_ops,
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.params = &rsci_rzg3e_port_params,
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};
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struct sci_of_data of_rsci_rzt2h_data = {
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.type = RSCI_PORT_SCIF16,
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.ops = &rsci_port_ops,
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@ -470,12 +705,19 @@ struct sci_of_data of_rsci_rzt2h_data = {
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#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
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static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *device,
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const char *opt)
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{
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return scix_early_console_setup(device, &of_rsci_rzg3e_data);
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}
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static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *device,
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const char *opt)
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{
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return scix_early_console_setup(device, &of_rsci_rzt2h_data);
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}
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OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_console_setup);
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OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_console_setup);
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#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
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@ -5,6 +5,7 @@
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#include "sh-sci-common.h"
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extern struct sci_of_data of_rsci_rzg3e_data;
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extern struct sci_of_data of_rsci_rzt2h_data;
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#endif /* __RSCI_H__ */
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@ -3329,6 +3329,7 @@ static int sci_init_single(struct platform_device *dev,
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sci_port->rx_trigger = 64;
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break;
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case PORT_SCIFA:
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case RSCI_PORT_SCIF32:
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sci_port->rx_trigger = 32;
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break;
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case PORT_SCIF:
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@ -3662,6 +3663,10 @@ static const struct of_device_id of_sci_match[] __maybe_unused = {
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.data = &of_sci_scif_rzv2h,
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},
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#ifdef CONFIG_SERIAL_RSCI
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{
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.compatible = "renesas,r9a09g047-rsci",
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.data = &of_rsci_rzg3e_data,
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},
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{
|
||||
.compatible = "renesas,r9a09g077-rsci",
|
||||
.data = &of_rsci_rzt2h_data,
|
||||
|
|
|
|||
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Reference in a new issue