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phy: starfive: jh7110-usb: Fix USB 2.0 host occasional detection failure

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JH7110 USB 2.0 host fails to detect USB 2.0 devices occasionally. With a
long time of debugging and testing, we found that setting Rx clock gating
control signal to normal power consumption mode can solve this problem.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20250422101244.51686-1-hal.feng@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Hal Feng 2025-04-22 18:12:44 +08:00 • committed by Vinod Koul
parent 9cf118aafd
commit 3f097adb9b
1 changed files with 7 additions and 0 deletions
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7
drivers/phy/starfive/phy-jh7110-usb.c
View file

@ -18,6 +18,8 @@
#include <linux/usb/of.h>
#define USB_125M_CLK_RATE 125000000
#define USB_CLK_MODE_OFF 0x0
#define USB_CLK_MODE_RX_NORMAL_PWR BIT(1)
#define USB_LS_KEEPALIVE_OFF 0x4
#define USB_LS_KEEPALIVE_ENABLE BIT(4)
@ -78,6 +80,7 @@ static int jh7110_usb2_phy_init(struct phy *_phy)
{
struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
int ret;
unsigned int val;
ret = clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE);
if (ret)
@ -87,6 +90,10 @@ static int jh7110_usb2_phy_init(struct phy *_phy)
if (ret)
return ret;
val = readl(phy->regs + USB_CLK_MODE_OFF);
val |= USB_CLK_MODE_RX_NORMAL_PWR;
writel(val, phy->regs + USB_CLK_MODE_OFF);
return 0;
}