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cxl: Simplify cxl_root_ops allocation and handling
A root port's callback handlers are collected in struct cxl_root_ops. The structure is dynamically allocated, though it contains only a single pointer in it. This also requires to check two pointers to check for the existance of a callback. Simplify the allocation, release and handler check by embedding the ops statically in struct cxl_root. Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Robert Richter <rrichter@amd.com> Link: https://patch.msgid.link/20260114164837.1076338-5-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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98ceb1a42d
commit
3e422caa40
4 changed files with 18 additions and 24 deletions
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@ -318,10 +318,6 @@ static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
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return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);
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}
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static const struct cxl_root_ops acpi_root_ops = {
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.qos_class = cxl_acpi_qos_class,
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};
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static void del_cxl_resource(struct resource *res)
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{
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if (!res)
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@ -923,9 +919,10 @@ static int cxl_acpi_probe(struct platform_device *pdev)
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cxl_res->end = -1;
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cxl_res->flags = IORESOURCE_MEM;
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cxl_root = devm_cxl_add_root(host, &acpi_root_ops);
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cxl_root = devm_cxl_add_root(host);
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if (IS_ERR(cxl_root))
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return PTR_ERR(cxl_root);
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cxl_root->ops.qos_class = cxl_acpi_qos_class;
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root_port = &cxl_root->port;
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rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
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@ -213,7 +213,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
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if (!cxl_root)
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return -ENODEV;
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if (!cxl_root->ops || !cxl_root->ops->qos_class)
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if (!cxl_root->ops.qos_class)
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return -EOPNOTSUPP;
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xa_for_each(dsmas_xa, index, dent) {
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@ -221,9 +221,9 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
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cxl_coordinates_combine(dent->coord, dent->cdat_coord, ep_c);
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dent->entries = 1;
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rc = cxl_root->ops->qos_class(cxl_root,
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&dent->coord[ACCESS_COORDINATE_CPU],
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1, &qos_class);
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rc = cxl_root->ops.qos_class(cxl_root,
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&dent->coord[ACCESS_COORDINATE_CPU],
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1, &qos_class);
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if (rc != 1)
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continue;
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@ -954,19 +954,15 @@ struct cxl_port *devm_cxl_add_port(struct device *host,
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, "CXL");
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struct cxl_root *devm_cxl_add_root(struct device *host,
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const struct cxl_root_ops *ops)
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struct cxl_root *devm_cxl_add_root(struct device *host)
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{
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struct cxl_root *cxl_root;
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struct cxl_port *port;
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port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
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if (IS_ERR(port))
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return ERR_CAST(port);
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cxl_root = to_cxl_root(port);
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cxl_root->ops = ops;
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return cxl_root;
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return to_cxl_root(port);
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_root, "CXL");
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@ -646,6 +646,14 @@ struct cxl_port {
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resource_size_t component_reg_phys;
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};
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struct cxl_root;
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struct cxl_root_ops {
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int (*qos_class)(struct cxl_root *cxl_root,
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struct access_coordinate *coord, int entries,
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int *qos_class);
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};
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/**
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* struct cxl_root - logical collection of root cxl_port items
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*
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@ -654,7 +662,7 @@ struct cxl_port {
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*/
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struct cxl_root {
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struct cxl_port port;
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const struct cxl_root_ops *ops;
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struct cxl_root_ops ops;
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};
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static inline struct cxl_root *
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@ -663,12 +671,6 @@ to_cxl_root(const struct cxl_port *port)
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return container_of(port, struct cxl_root, port);
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}
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struct cxl_root_ops {
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int (*qos_class)(struct cxl_root *cxl_root,
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struct access_coordinate *coord, int entries,
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int *qos_class);
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};
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static inline struct cxl_dport *
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cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
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{
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@ -782,8 +784,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host,
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struct device *uport_dev,
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resource_size_t component_reg_phys,
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struct cxl_dport *parent_dport);
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struct cxl_root *devm_cxl_add_root(struct device *host,
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const struct cxl_root_ops *ops);
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struct cxl_root *devm_cxl_add_root(struct device *host);
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struct cxl_root *find_cxl_root(struct cxl_port *port);
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DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev))
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