archives/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-03-08 01:04:41 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

raid6: test: Add support for RISC-V

Browse source 
Add RISC-V code to be compiled to allow the userspace raid6test program
to be built and run on RISC-V.

Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://patch.msgid.link/20250718072711.3865118-6-zhangchunyan@iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Chunyan Zhang 2025-11-17 21:19:25 -07:00 • committed by Paul Walmsley
parent 3c58d7a513
commit 3ac022bf38
1 changed files with 8 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

8
lib/raid6/test/Makefile
View file

@ -35,6 +35,11 @@ ifeq ($(ARCH),aarch64)
HAS_NEON = yes
endif
ifeq ($(findstring riscv,$(ARCH)),riscv)
CFLAGS += -I../../../arch/riscv/include -DCONFIG_RISCV=1
HAS_RVV = yes
endif
ifeq ($(findstring ppc,$(ARCH)),ppc)
CFLAGS += -I../../../arch/powerpc/include
HAS_ALTIVEC := $(shell printf '$(pound)include <altivec.h>\nvector int a;\n' |\
@ -63,6 +68,9 @@ else ifeq ($(HAS_ALTIVEC),yes)
vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o
else ifeq ($(ARCH),loongarch64)
OBJS += loongarch_simd.o recov_loongarch_simd.o
else ifeq ($(HAS_RVV),yes)
OBJS += rvv.o recov_rvv.o
CFLAGS += -DCONFIG_RISCV_ISA_V=1
endif
.c.o: