spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays

Change spi-rx-bus-width and spi-tx-bus-width properties from single
uint32 values to arrays of uint32 values. This allows describing SPI
peripherals connected to controllers that have multiple data lanes for
receiving or transmitting two or more words in parallel.

Each index in the array corresponds to a physical data lane (one or more
wires depending on the bus width). Additional mapping properties will be
needed in cases where a lane on the controller or peripheral is skipped.

Bindings that make use of this property are updated in the same commit
to avoid validation errors.

The adi,ad4030 binding can now better describe the chips multi-lane
capabilities, so that binding is refined and gets a new example.

Converting from single uint32 to array of uint32 does not break .dts/
.dtb files since there is no difference between specifying a single
uint32 value and an array with a single uint32 value in devicetree.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-1-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
David Lechner 2026-01-23 14:37:24 -06:00 committed by Mark Brown
parent b2f0678308
commit 37bb4033e4
No known key found for this signature in database
GPG key ID: 24D68B725D5487D0
8 changed files with 83 additions and 19 deletions

View file

@ -34,8 +34,9 @@ properties:
spi-cpol: true
spi-rx-bus-width:
minimum: 0
maximum: 1
items:
minimum: 0
maximum: 1
dc-gpios:
maxItems: 1

View file

@ -37,7 +37,15 @@ properties:
maximum: 102040816
spi-rx-bus-width:
enum: [1, 2, 4]
maxItems: 2
# all lanes must have the same width
oneOf:
- contains:
const: 1
- contains:
const: 2
- contains:
const: 4
vdd-5v-supply: true
vdd-1v8-supply: true
@ -88,6 +96,18 @@ oneOf:
unevaluatedProperties: false
allOf:
- if:
properties:
compatible:
enum:
- adi,ad4030-24
- adi,ad4032-24
then:
properties:
spi-rx-bus-width:
maxItems: 1
examples:
- |
#include <dt-bindings/gpio/gpio.h>
@ -108,3 +128,23 @@ examples:
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
};
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "adi,ad4630-24";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>, <4>;
vdd-5v-supply = <&supply_5V>;
vdd-1v8-supply = <&supply_1_8V>;
vio-supply = <&supply_1_8V>;
ref-supply = <&supply_5V>;
cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
};

View file

@ -38,8 +38,9 @@ properties:
spi-cpha: true
spi-rx-bus-width:
minimum: 1
maximum: 4
items:
minimum: 1
maximum: 4
avdd-supply:
description: Analog power supply.

View file

@ -55,10 +55,12 @@ patternProperties:
maximum: 4
spi-rx-bus-width:
const: 1
items:
- const: 1
spi-tx-bus-width:
const: 1
items:
- const: 1
required:
- compatible

View file

@ -77,10 +77,12 @@ patternProperties:
maximum: 4
spi-rx-bus-width:
const: 1
items:
- const: 1
spi-tx-bus-width:
const: 1
items:
- const: 1
required:
- compatible

View file

@ -45,10 +45,12 @@ patternProperties:
properties:
spi-rx-bus-width:
enum: [1, 4]
items:
- enum: [1, 4]
spi-tx-bus-width:
enum: [1, 4]
items:
- enum: [1, 4]
allOf:
- $ref: spi-controller.yaml#

View file

@ -54,10 +54,12 @@ patternProperties:
properties:
spi-rx-bus-width:
enum: [1, 2, 4]
items:
- enum: [1, 2, 4]
spi-tx-bus-width:
enum: [1, 2, 4]
items:
- enum: [1, 2, 4]
required:
- compatible

View file

@ -64,9 +64,16 @@ properties:
description:
Bus width to the SPI bus used for read transfers.
If 0 is provided, then no RX will be possible on this device.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 4, 8]
default: 1
Some SPI peripherals and controllers may have multiple data lanes for
receiving two or more words at the same time. If this is the case, each
index in the array represents the lane on both the SPI peripheral and
controller. Additional mapping properties may be needed if a lane is
skipped on either side.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
enum: [0, 1, 2, 4, 8]
default: [1]
spi-rx-delay-us:
description:
@ -81,9 +88,16 @@ properties:
description:
Bus width to the SPI bus used for write transfers.
If 0 is provided, then no TX will be possible on this device.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 4, 8]
default: 1
Some SPI peripherals and controllers may have multiple data lanes for
transmitting two or more words at the same time. If this is the case, each
index in the array represents the lane on both the SPI peripheral and
controller. Additional mapping properties may be needed if a lane is
skipped on either side.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
enum: [0, 1, 2, 4, 8]
default: [1]
spi-tx-delay-us:
description: