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spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays
Change spi-rx-bus-width and spi-tx-bus-width properties from single uint32 values to arrays of uint32 values. This allows describing SPI peripherals connected to controllers that have multiple data lanes for receiving or transmitting two or more words in parallel. Each index in the array corresponds to a physical data lane (one or more wires depending on the bus width). Additional mapping properties will be needed in cases where a lane on the controller or peripheral is skipped. Bindings that make use of this property are updated in the same commit to avoid validation errors. The adi,ad4030 binding can now better describe the chips multi-lane capabilities, so that binding is refined and gets a new example. Converting from single uint32 to array of uint32 does not break .dts/ .dtb files since there is no difference between specifying a single uint32 value and an array with a single uint32 value in devicetree. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-1-12af183c06eb@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
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8 changed files with 83 additions and 19 deletions
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@ -34,8 +34,9 @@ properties:
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spi-cpol: true
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spi-rx-bus-width:
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minimum: 0
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maximum: 1
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items:
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minimum: 0
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maximum: 1
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dc-gpios:
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maxItems: 1
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@ -37,7 +37,15 @@ properties:
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maximum: 102040816
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spi-rx-bus-width:
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enum: [1, 2, 4]
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maxItems: 2
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# all lanes must have the same width
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oneOf:
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- contains:
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const: 1
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- contains:
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const: 2
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- contains:
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const: 4
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vdd-5v-supply: true
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vdd-1v8-supply: true
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@ -88,6 +96,18 @@ oneOf:
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unevaluatedProperties: false
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- adi,ad4030-24
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- adi,ad4032-24
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then:
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properties:
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spi-rx-bus-width:
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maxItems: 1
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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@ -108,3 +128,23 @@ examples:
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reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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};
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};
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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adc@0 {
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compatible = "adi,ad4630-24";
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reg = <0>;
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spi-max-frequency = <80000000>;
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spi-rx-bus-width = <4>, <4>;
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vdd-5v-supply = <&supply_5V>;
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vdd-1v8-supply = <&supply_1_8V>;
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vio-supply = <&supply_1_8V>;
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ref-supply = <&supply_5V>;
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cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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};
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};
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@ -38,8 +38,9 @@ properties:
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spi-cpha: true
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spi-rx-bus-width:
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minimum: 1
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maximum: 4
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items:
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minimum: 1
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maximum: 4
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avdd-supply:
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description: Analog power supply.
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@ -55,10 +55,12 @@ patternProperties:
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maximum: 4
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spi-rx-bus-width:
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const: 1
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items:
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- const: 1
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spi-tx-bus-width:
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const: 1
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items:
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- const: 1
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required:
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- compatible
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@ -77,10 +77,12 @@ patternProperties:
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maximum: 4
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spi-rx-bus-width:
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const: 1
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items:
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- const: 1
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spi-tx-bus-width:
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const: 1
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items:
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- const: 1
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required:
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- compatible
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@ -45,10 +45,12 @@ patternProperties:
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properties:
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spi-rx-bus-width:
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enum: [1, 4]
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items:
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- enum: [1, 4]
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spi-tx-bus-width:
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enum: [1, 4]
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items:
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- enum: [1, 4]
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allOf:
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- $ref: spi-controller.yaml#
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@ -54,10 +54,12 @@ patternProperties:
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properties:
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spi-rx-bus-width:
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enum: [1, 2, 4]
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items:
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- enum: [1, 2, 4]
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spi-tx-bus-width:
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enum: [1, 2, 4]
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items:
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- enum: [1, 2, 4]
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required:
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- compatible
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@ -64,9 +64,16 @@ properties:
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description:
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Bus width to the SPI bus used for read transfers.
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If 0 is provided, then no RX will be possible on this device.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 4, 8]
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default: 1
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Some SPI peripherals and controllers may have multiple data lanes for
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receiving two or more words at the same time. If this is the case, each
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index in the array represents the lane on both the SPI peripheral and
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controller. Additional mapping properties may be needed if a lane is
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skipped on either side.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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enum: [0, 1, 2, 4, 8]
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default: [1]
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spi-rx-delay-us:
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description:
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@ -81,9 +88,16 @@ properties:
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description:
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Bus width to the SPI bus used for write transfers.
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If 0 is provided, then no TX will be possible on this device.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 4, 8]
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default: 1
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Some SPI peripherals and controllers may have multiple data lanes for
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transmitting two or more words at the same time. If this is the case, each
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index in the array represents the lane on both the SPI peripheral and
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controller. Additional mapping properties may be needed if a lane is
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skipped on either side.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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enum: [0, 1, 2, 4, 8]
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default: [1]
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spi-tx-delay-us:
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description:
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