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dt-bindings: clk: rs9: Fix DIF pattern match

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The pattern match [0-19] is incorrect and does not cover range of 0..19,
use pattern 1?[0-9] to cover range 0..19 instead. Update the example to
validate all parts of the pattern match and prevent such failures in the
future.

Fixes: 26c1bc67aa ("dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Marek Vasut 2025-10-14 12:46:03 +02:00 • committed by Stephen Boyd
parent 37eb3349a3
commit 341d72ebc2
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1 changed files with 10 additions and 1 deletions
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11
Documentation/devicetree/bindings/clock/renesas,9series.yaml
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@ -62,7 +62,7 @@ properties:
description: Output clock down spread in pcm (1/1000 of percent)
patternProperties:
"^DIF[0-19]$":
"^DIF1?[0-9]$":
type: object
description:
Description of one of the outputs (DIF0..DIF19).
@ -107,6 +107,15 @@ examples:
DIF0 {
renesas,slew-rate = <3000000>;
};
/* Not present on 9FGV0241, used for DT validation only */
DIF2 {
renesas,slew-rate = <2000000>;
};
DIF19 {
renesas,slew-rate = <3000000>;
};
};
};