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drm/amdgpu: Update MES VM_CNTX_CNTL for XNACK off for GFX 12.1

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Currently, we do not turn off retry faults in VM_CONTEXT_CNTL value
when passing it to MES if XNACK is off. This creates a situation where
XNACK is disabled in SQ but enabled in UTCL2, which is not recommended.
As a result, turn off/on retry faults in both SQ and UTCL2 when passing
vm_context_cntl value to MES if XNACK is disabled/enabled.

Suggested-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi 2025-04-28 22:08:10 -04:00 • committed by Alex Deucher
parent cc52af1a96
commit 3235a5b723
5 changed files with 14 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

1
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
View file

@ -254,6 +254,7 @@ struct mes_add_queue_input {
uint32_t queue_size;
uint32_t exclusively_scheduled;
uint32_t sh_mem_config_data;
uint32_t vm_cntx_cntl;
};
struct mes_remove_queue_input {

5
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
View file

@ -286,10 +286,7 @@ static int convert_to_mes_queue_type(int queue_type)
static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes,
struct mes_add_queue_input *input)
{
struct amdgpu_device *adev = mes->adev;
union MESAPI__ADD_QUEUE mes_add_queue_pkt;
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
int xcc_id = input->xcc_id;
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
@ -322,7 +319,7 @@ static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes,
mes_add_queue_pkt.queue_type =
convert_to_mes_queue_type(input->queue_type);
mes_add_queue_pkt.paging = input->paging;
mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
mes_add_queue_pkt.vm_context_cntl = input->vm_cntx_cntl;
mes_add_queue_pkt.gws_base = input->gws_base;
mes_add_queue_pkt.gws_size = input->gws_size;
mes_add_queue_pkt.trap_handler_addr = input->tba_addr;

1
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
View file

@ -256,6 +256,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
queue_input.exclusively_scheduled = q->properties.is_gws;
queue_input.sh_mem_config_data = qpd->sh_mem_config;
queue_input.vm_cntx_cntl = qpd->vm_cntx_cntl;
amdgpu_mes_lock(&adev->mes);
r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);

12
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
View file

@ -52,8 +52,11 @@ static int update_qpd_v12_1(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
struct kfd_process_device *pdd;
struct amdgpu_device *adev = dqm->dev->adev;
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
pdd = qpd_to_pdd(qpd);
qpd->vm_cntx_cntl = hub->vm_cntx_cntl;
/* check if sh_mem_config register already configured */
if (qpd->sh_mem_config == 0) {
@ -69,10 +72,15 @@ static int update_qpd_v12_1(struct device_queue_manager *dqm,
}
if (KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev)) {
if (!pdd->process->xnack_enabled)
if (!pdd->process->xnack_enabled) {
qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
else
qpd->vm_cntx_cntl &=
~(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT);
} else {
qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT);
qpd->vm_cntx_cntl |=
(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT);
}
}
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);

1
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
View file

@ -697,6 +697,7 @@ struct qcm_process_device {
uint32_t num_gws;
uint32_t num_oac;
uint32_t sh_hidden_private_base;
uint32_t vm_cntx_cntl;
/* CWSR memory */
struct kgd_mem *cwsr_mem;