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dt-bindings: clock: qcom: document Kaanapali DISPCC clock controller

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Document device tree bindings for display clock controller for
Qualcomm Kaanapali SoC.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-4-8e10adc236a8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das 2026-01-07 15:13:07 +05:30 • committed by Bjorn Andersson
parent 8f0b4cce44
commit 322aad122c
2 changed files with 111 additions and 0 deletions
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2
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
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@ -15,6 +15,7 @@ description: |
domains on SM8550, SM8650, SM8750 and few other platforms.
See also:
- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-dispcc
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc

109
include/dt-bindings/clock/qcom,kaanapali-dispcc.h Normal file
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@ -0,0 +1,109 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H
/* DISP_CC clocks */
#define DISP_CC_ESYNC0_CLK 0
#define DISP_CC_ESYNC0_CLK_SRC 1
#define DISP_CC_ESYNC1_CLK 2
#define DISP_CC_ESYNC1_CLK_SRC 3
#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
#define DISP_CC_MDSS_AHB1_CLK 5
#define DISP_CC_MDSS_AHB_CLK 6
#define DISP_CC_MDSS_AHB_CLK_SRC 7
#define DISP_CC_MDSS_AHB_SWI_CLK 8
#define DISP_CC_MDSS_AHB_SWI_DIV_CLK_SRC 9
#define DISP_CC_MDSS_BYTE0_CLK 10
#define DISP_CC_MDSS_BYTE0_CLK_SRC 11
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 12
#define DISP_CC_MDSS_BYTE0_INTF_CLK 13
#define DISP_CC_MDSS_BYTE1_CLK 14
#define DISP_CC_MDSS_BYTE1_CLK_SRC 15
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 16
#define DISP_CC_MDSS_BYTE1_INTF_CLK 17
#define DISP_CC_MDSS_DPTX0_AUX_CLK 18
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 20
#define DISP_CC_MDSS_DPTX0_LINK_CLK 21
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 22
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 23
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 24
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 25
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 26
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 27
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 28
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 29
#define DISP_CC_MDSS_DPTX1_AUX_CLK 30
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 31
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 32
#define DISP_CC_MDSS_DPTX1_LINK_CLK 33
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 34
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 35
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 36
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 37
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 38
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 39
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 40
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 41
#define DISP_CC_MDSS_DPTX2_AUX_CLK 42
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 43
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 44
#define DISP_CC_MDSS_DPTX2_LINK_CLK 45
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 46
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 47
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 48
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 49
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 50
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 51
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 52
#define DISP_CC_MDSS_DPTX3_AUX_CLK 53
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 54
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 55
#define DISP_CC_MDSS_DPTX3_LINK_CLK 56
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 57
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 58
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 59
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 60
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 61
#define DISP_CC_MDSS_ESC0_CLK 62
#define DISP_CC_MDSS_ESC0_CLK_SRC 63
#define DISP_CC_MDSS_ESC1_CLK 64
#define DISP_CC_MDSS_ESC1_CLK_SRC 65
#define DISP_CC_MDSS_MDP1_CLK 66
#define DISP_CC_MDSS_MDP_CLK 67
#define DISP_CC_MDSS_MDP_CLK_SRC 68
#define DISP_CC_MDSS_MDP_LUT1_CLK 69
#define DISP_CC_MDSS_MDP_LUT_CLK 70
#define DISP_CC_MDSS_MDP_SS_IP_CLK 71
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 72
#define DISP_CC_MDSS_PCLK0_CLK 73
#define DISP_CC_MDSS_PCLK0_CLK_SRC 74
#define DISP_CC_MDSS_PCLK1_CLK 75
#define DISP_CC_MDSS_PCLK1_CLK_SRC 76
#define DISP_CC_MDSS_PCLK2_CLK 77
#define DISP_CC_MDSS_PCLK2_CLK_SRC 78
#define DISP_CC_MDSS_VSYNC1_CLK 79
#define DISP_CC_MDSS_VSYNC_CLK 80
#define DISP_CC_MDSS_VSYNC_CLK_SRC 81
#define DISP_CC_OSC_CLK 82
#define DISP_CC_OSC_CLK_SRC 83
#define DISP_CC_PLL0 84
#define DISP_CC_PLL1 85
#define DISP_CC_PLL2 86
#define DISP_CC_SLEEP_CLK 87
#define DISP_CC_XO_CLK 88
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif