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selftests: riscv: verify ptrace rejects invalid vector csr inputs
Add a test to v_ptrace test suite to verify that ptrace rejects the invalid input combinations of vector csr registers. Use kselftest fixture variants to create multiple invalid inputs for the test. Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Tested-by: Andy Chiu <andybnac@gmail.com> Link: https://patch.msgid.link/20251214163537.1054292-9-geomatsi@gmail.com [pjw@kernel.org: cleaned up some checkpatch issues] Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Sergey Matyukevich
Paul Walmsley
parent
3789d5eecd
commit
30eb191c89
1 changed files with 317 additions and 0 deletions
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@ -334,4 +334,321 @@ TEST(ptrace_v_syscall_clobbering)
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}
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}
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FIXTURE(v_csr_invalid)
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{
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};
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FIXTURE_SETUP(v_csr_invalid)
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{
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}
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FIXTURE_TEARDOWN(v_csr_invalid)
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{
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}
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#define VECTOR_1_0 BIT(0)
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#define XTHEAD_VECTOR_0_7 BIT(1)
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#define vector_test(x) ((x) & VECTOR_1_0)
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#define xthead_test(x) ((x) & XTHEAD_VECTOR_0_7)
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/* modifications of the initial vsetvli settings */
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FIXTURE_VARIANT(v_csr_invalid)
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{
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unsigned long vstart;
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unsigned long vl;
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unsigned long vtype;
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unsigned long vcsr;
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unsigned long vlenb_mul;
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unsigned long vlenb_min;
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unsigned long vlenb_max;
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unsigned long spec;
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};
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/* unexpected vlenb value */
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FIXTURE_VARIANT_ADD(v_csr_invalid, new_vlenb)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x3,
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.vcsr = 0x0,
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.vlenb_mul = 0x2,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,
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};
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/* invalid reserved bits in vcsr */
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FIXTURE_VARIANT_ADD(v_csr_invalid, vcsr_invalid_reserved_bits)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x3,
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.vcsr = 0x1UL << 8,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,
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};
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/* invalid reserved bits in vtype */
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FIXTURE_VARIANT_ADD(v_csr_invalid, vtype_invalid_reserved_bits)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = (0x1UL << 8) | 0x3,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,
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};
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/* set vill bit */
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FIXTURE_VARIANT_ADD(v_csr_invalid, invalid_vill_bit)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = (0x1UL << (__riscv_xlen - 1)) | 0x3,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0 | XTHEAD_VECTOR_0_7,
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};
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/* reserved vsew value: vsew > 3 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vsew)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x4UL << 3,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0,
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};
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/* XTheadVector: unsupported non-zero VEDIV value */
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FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vediv)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x3UL << 5,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = XTHEAD_VECTOR_0_7,
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};
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/* reserved vlmul value: vlmul == 4 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vlmul)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x4,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x0,
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.spec = VECTOR_1_0,
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};
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/* invalid fractional LMUL for VLEN <= 256: LMUL= 1/8, SEW = 64 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, frac_lmul1)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x1d,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x20,
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.spec = VECTOR_1_0,
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};
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/* invalid integral LMUL for VLEN <= 16: LMUL= 2, SEW = 64 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, int_lmul1)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0x19,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x2,
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.spec = VECTOR_1_0,
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};
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/* XTheadVector: invalid integral LMUL for VLEN <= 16: LMUL= 2, SEW = 64 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, int_lmul2)
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{
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.vstart = 0x0,
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.vl = 0x0,
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.vtype = 0xd,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x2,
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.spec = XTHEAD_VECTOR_0_7,
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};
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/* invalid VL for VLEN <= 128: LMUL= 2, SEW = 64, VL = 8 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, vl1)
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{
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.vstart = 0x0,
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.vl = 0x8,
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.vtype = 0x19,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x10,
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.spec = VECTOR_1_0,
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};
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/* XTheadVector: invalid VL for VLEN <= 128: LMUL= 2, SEW = 64, VL = 8 */
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FIXTURE_VARIANT_ADD(v_csr_invalid, vl2)
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{
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.vstart = 0x0,
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.vl = 0x8,
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.vtype = 0xd,
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.vcsr = 0x0,
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.vlenb_mul = 0x1,
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.vlenb_min = 0x0,
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.vlenb_max = 0x10,
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.spec = XTHEAD_VECTOR_0_7,
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};
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TEST_F(v_csr_invalid, ptrace_v_invalid_values)
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{
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unsigned long vlenb;
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pid_t pid;
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if (!is_vector_supported() && !is_xtheadvector_supported())
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SKIP(return, "Vectors not supported");
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if (is_vector_supported() && !vector_test(variant->spec))
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SKIP(return, "Test not supported for Vector");
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if (is_xtheadvector_supported() && !xthead_test(variant->spec))
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SKIP(return, "Test not supported for XTheadVector");
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vlenb = get_vr_len();
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if (variant->vlenb_min) {
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if (vlenb < variant->vlenb_min)
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SKIP(return, "This test does not support VLEN < %lu\n",
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variant->vlenb_min * 8);
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}
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if (variant->vlenb_max) {
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if (vlenb > variant->vlenb_max)
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SKIP(return, "This test does not support VLEN > %lu\n",
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variant->vlenb_max * 8);
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}
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chld_lock = 1;
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pid = fork();
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ASSERT_LE(0, pid)
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TH_LOG("fork: %m");
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if (pid == 0) {
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unsigned long vl;
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while (chld_lock == 1)
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asm volatile("" : : "g"(chld_lock) : "memory");
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if (is_xtheadvector_supported()) {
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asm volatile (
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// 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli
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// vsetvli t4, x0, e16, m2, d1
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".4byte 0b00000000010100000111111011010111\n"
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"mv %[new_vl], t4\n"
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: [new_vl] "=r" (vl) : : "t4");
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} else {
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asm volatile (
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".option push\n"
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".option arch, +zve32x\n"
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"vsetvli %[new_vl], x0, e16, m2, tu, mu\n"
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".option pop\n"
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: [new_vl] "=r"(vl) : : );
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}
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while (1) {
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asm volatile (
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".option push\n"
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".option norvc\n"
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"ebreak\n"
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"nop\n"
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".option pop\n");
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}
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} else {
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struct __riscv_v_regset_state *regset_data;
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size_t regset_size;
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struct iovec iov;
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int status;
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int ret;
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/* attach */
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ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* unlock */
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ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0));
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/* resume and wait for the 1st ebreak */
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ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
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ASSERT_EQ(pid, waitpid(pid, &status, 0));
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ASSERT_TRUE(WIFSTOPPED(status));
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/* read tracee vector csr regs using ptrace GETREGSET */
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regset_size = sizeof(*regset_data) + vlenb * 32;
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regset_data = calloc(1, regset_size);
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iov.iov_base = regset_data;
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iov.iov_len = regset_size;
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ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov));
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/* verify initial vsetvli settings */
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if (is_xtheadvector_supported())
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EXPECT_EQ(5UL, regset_data->vtype);
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else
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EXPECT_EQ(9UL, regset_data->vtype);
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EXPECT_EQ(regset_data->vlenb, regset_data->vl);
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EXPECT_EQ(vlenb, regset_data->vlenb);
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EXPECT_EQ(0UL, regset_data->vstart);
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EXPECT_EQ(0UL, regset_data->vcsr);
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/* apply invalid settings from fixture variants */
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regset_data->vlenb *= variant->vlenb_mul;
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regset_data->vstart = variant->vstart;
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regset_data->vtype = variant->vtype;
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regset_data->vcsr = variant->vcsr;
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regset_data->vl = variant->vl;
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iov.iov_base = regset_data;
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iov.iov_len = regset_size;
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errno = 0;
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ret = ptrace(PTRACE_SETREGSET, pid, NT_RISCV_VECTOR, &iov);
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ASSERT_EQ(errno, EINVAL);
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ASSERT_EQ(ret, -1);
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/* cleanup */
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ASSERT_EQ(0, kill(pid, SIGKILL));
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}
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}
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TEST_HARNESS_MAIN
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