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Merge branch '20260105-kvmrprocv10-v10-0-022e96815380@oss.qualcomm.com' into drivers-for-6.20
Merge the support for loading and managing the TrustZone-based remote processors found in the Glymur platform through a topic branch, as it's a mix of qcom-soc and remoteproc patches.
This commit is contained in:
Bjorn Andersson
commit
29b3a61e4e
7 changed files with 536 additions and 116 deletions
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|
@ -44,6 +44,9 @@ properties:
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- const: stop-ack
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- const: shutdown-ack
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iommus:
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maxItems: 1
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power-domains:
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minItems: 1
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maxItems: 3
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|
|
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@ -27,6 +27,7 @@
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#include <linux/of_reserved_mem.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/remoteproc.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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@ -119,6 +120,8 @@ enum qcom_scm_qseecom_tz_cmd_info {
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QSEECOM_TZ_CMD_INFO_VERSION = 3,
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};
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#define RSCTABLE_BUFFER_NOT_SUFFICIENT 20
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#define QSEECOM_MAX_APP_NAME_SIZE 64
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#define SHMBRIDGE_RESULT_NOTSUPP 4
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@ -568,16 +571,105 @@ static void qcom_scm_set_download_mode(u32 dload_mode)
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dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
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}
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/**
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* devm_qcom_scm_pas_context_alloc() - Allocate peripheral authentication service
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* context for a given peripheral
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*
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* PAS context is device-resource managed, so the caller does not need
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* to worry about freeing the context memory.
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*
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* @dev: PAS firmware device
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* @pas_id: peripheral authentication service id
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* @mem_phys: Subsystem reserve memory start address
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* @mem_size: Subsystem reserve memory size
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*
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* Returns: The new PAS context, or ERR_PTR() on failure.
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*/
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struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev,
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u32 pas_id,
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phys_addr_t mem_phys,
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size_t mem_size)
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{
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struct qcom_scm_pas_context *ctx;
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ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return ERR_PTR(-ENOMEM);
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ctx->dev = dev;
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ctx->pas_id = pas_id;
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ctx->mem_phys = mem_phys;
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ctx->mem_size = mem_size;
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return ctx;
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}
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EXPORT_SYMBOL_GPL(devm_qcom_scm_pas_context_alloc);
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static int __qcom_scm_pas_init_image(u32 pas_id, dma_addr_t mdata_phys,
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struct qcom_scm_res *res)
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{
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
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.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
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.args[0] = pas_id,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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int ret;
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ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = qcom_scm_bw_enable();
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if (ret)
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goto disable_clk;
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desc.args[1] = mdata_phys;
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ret = qcom_scm_call(__scm->dev, &desc, res);
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qcom_scm_bw_disable();
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disable_clk:
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qcom_scm_clk_disable();
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return ret;
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}
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static int qcom_scm_pas_prep_and_init_image(struct qcom_scm_pas_context *ctx,
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const void *metadata, size_t size)
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{
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struct qcom_scm_res res;
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phys_addr_t mdata_phys;
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void *mdata_buf;
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int ret;
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mdata_buf = qcom_tzmem_alloc(__scm->mempool, size, GFP_KERNEL);
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if (!mdata_buf)
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return -ENOMEM;
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memcpy(mdata_buf, metadata, size);
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mdata_phys = qcom_tzmem_to_phys(mdata_buf);
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ret = __qcom_scm_pas_init_image(ctx->pas_id, mdata_phys, &res);
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if (ret < 0)
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qcom_tzmem_free(mdata_buf);
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else
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ctx->ptr = mdata_buf;
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return ret ? : res.result[0];
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}
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/**
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* qcom_scm_pas_init_image() - Initialize peripheral authentication service
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* state machine for a given peripheral, using the
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* metadata
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* @peripheral: peripheral id
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* @pas_id: peripheral authentication service id
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* @metadata: pointer to memory containing ELF header, program header table
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* and optional blob of data used for authenticating the metadata
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* and the rest of the firmware
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* @size: size of the metadata
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* @ctx: optional metadata context
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* @ctx: optional pas context
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*
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* Return: 0 on success.
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*
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@ -585,20 +677,16 @@ static void qcom_scm_set_download_mode(u32 dload_mode)
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* track the metadata allocation, this needs to be released by invoking
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* qcom_scm_pas_metadata_release() by the caller.
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*/
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int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
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struct qcom_scm_pas_metadata *ctx)
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int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
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struct qcom_scm_pas_context *ctx)
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{
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struct qcom_scm_res res;
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dma_addr_t mdata_phys;
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void *mdata_buf;
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
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.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
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.args[0] = peripheral,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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if (ctx && ctx->use_tzmem)
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return qcom_scm_pas_prep_and_init_image(ctx, metadata, size);
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/*
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* During the scm call memory protection will be enabled for the meta
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@ -619,23 +707,7 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
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memcpy(mdata_buf, metadata, size);
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ret = qcom_scm_clk_enable();
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if (ret)
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goto out;
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ret = qcom_scm_bw_enable();
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if (ret)
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goto disable_clk;
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desc.args[1] = mdata_phys;
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ret = qcom_scm_call(__scm->dev, &desc, &res);
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qcom_scm_bw_disable();
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disable_clk:
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qcom_scm_clk_disable();
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out:
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ret = __qcom_scm_pas_init_image(pas_id, mdata_phys, &res);
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if (ret < 0 || !ctx) {
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dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
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} else if (ctx) {
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@ -650,38 +722,39 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image);
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/**
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* qcom_scm_pas_metadata_release() - release metadata context
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* @ctx: metadata context
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* @ctx: pas context
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*/
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void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx)
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void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx)
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{
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if (!ctx->ptr)
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return;
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dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys);
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if (ctx->use_tzmem)
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qcom_tzmem_free(ctx->ptr);
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else
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dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys);
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ctx->ptr = NULL;
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ctx->phys = 0;
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ctx->size = 0;
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}
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EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release);
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/**
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* qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
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* for firmware loading
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* @peripheral: peripheral id
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* @pas_id: peripheral authentication service id
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* @addr: start address of memory area to prepare
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* @size: size of the memory area to prepare
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
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int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size)
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{
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
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.arginfo = QCOM_SCM_ARGS(3),
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.args[0] = peripheral,
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.args[0] = pas_id,
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.args[1] = addr,
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.args[2] = size,
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.owner = ARM_SMCCC_OWNER_SIP,
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@ -706,21 +779,189 @@ disable_clk:
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}
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EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup);
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static void *__qcom_scm_pas_get_rsc_table(u32 pas_id, void *input_rt_tzm,
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size_t input_rt_size,
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size_t *output_rt_size)
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{
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_GET_RSCTABLE,
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.arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RO, QCOM_SCM_VAL,
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QCOM_SCM_RW, QCOM_SCM_VAL),
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.args[0] = pas_id,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
|
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struct qcom_scm_res res;
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void *output_rt_tzm;
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int ret;
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output_rt_tzm = qcom_tzmem_alloc(__scm->mempool, *output_rt_size, GFP_KERNEL);
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if (!output_rt_tzm)
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return ERR_PTR(-ENOMEM);
|
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|
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desc.args[1] = qcom_tzmem_to_phys(input_rt_tzm);
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desc.args[2] = input_rt_size;
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desc.args[3] = qcom_tzmem_to_phys(output_rt_tzm);
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desc.args[4] = *output_rt_size;
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/*
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* Whether SMC fail or pass, res.result[2] will hold actual resource table
|
||||
* size.
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*
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* If passed 'output_rt_size' buffer size is not sufficient to hold the
|
||||
* resource table TrustZone sends, response code in res.result[1] as
|
||||
* RSCTABLE_BUFFER_NOT_SUFFICIENT so that caller can retry this SMC call
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||||
* with output_rt_tzm buffer with res.result[2] size however, It should not
|
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* be of unresonable size.
|
||||
*/
|
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ret = qcom_scm_call(__scm->dev, &desc, &res);
|
||||
if (!ret && res.result[2] > SZ_1G) {
|
||||
ret = -E2BIG;
|
||||
goto free_output_rt;
|
||||
}
|
||||
|
||||
*output_rt_size = res.result[2];
|
||||
if (ret && res.result[1] == RSCTABLE_BUFFER_NOT_SUFFICIENT)
|
||||
ret = -EOVERFLOW;
|
||||
|
||||
free_output_rt:
|
||||
if (ret)
|
||||
qcom_tzmem_free(output_rt_tzm);
|
||||
|
||||
return ret ? ERR_PTR(ret) : output_rt_tzm;
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_scm_pas_get_rsc_table() - Retrieve the resource table in passed output buffer
|
||||
* for a given peripheral.
|
||||
*
|
||||
* Qualcomm remote processor may rely on both static and dynamic resources for
|
||||
* its functionality. Static resources typically refer to memory-mapped addresses
|
||||
* required by the subsystem and are often embedded within the firmware binary
|
||||
* and dynamic resources, such as shared memory in DDR etc., are determined at
|
||||
* runtime during the boot process.
|
||||
*
|
||||
* On Qualcomm Technologies devices, it's possible that static resources are not
|
||||
* embedded in the firmware binary and instead are provided by TrustZone However,
|
||||
* dynamic resources are always expected to come from TrustZone. This indicates
|
||||
* that for Qualcomm devices, all resources (static and dynamic) will be provided
|
||||
* by TrustZone via the SMC call.
|
||||
*
|
||||
* If the remote processor firmware binary does contain static resources, they
|
||||
* should be passed in input_rt. These will be forwarded to TrustZone for
|
||||
* authentication. TrustZone will then append the dynamic resources and return
|
||||
* the complete resource table in output_rt_tzm.
|
||||
*
|
||||
* If the remote processor firmware binary does not include a resource table,
|
||||
* the caller of this function should set input_rt as NULL and input_rt_size
|
||||
* as zero respectively.
|
||||
*
|
||||
* More about documentation on resource table data structures can be found in
|
||||
* include/linux/remoteproc.h
|
||||
*
|
||||
* @ctx: PAS context
|
||||
* @pas_id: peripheral authentication service id
|
||||
* @input_rt: resource table buffer which is present in firmware binary
|
||||
* @input_rt_size: size of the resource table present in firmware binary
|
||||
* @output_rt_size: TrustZone expects caller should pass worst case size for
|
||||
* the output_rt_tzm.
|
||||
*
|
||||
* Return:
|
||||
* On success, returns a pointer to the allocated buffer containing the final
|
||||
* resource table and output_rt_size will have actual resource table size from
|
||||
* TrustZone. The caller is responsible for freeing the buffer. On failure,
|
||||
* returns ERR_PTR(-errno).
|
||||
*/
|
||||
struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx,
|
||||
void *input_rt,
|
||||
size_t input_rt_size,
|
||||
size_t *output_rt_size)
|
||||
{
|
||||
struct resource_table empty_rsc = {};
|
||||
size_t size = SZ_16K;
|
||||
void *output_rt_tzm;
|
||||
void *input_rt_tzm;
|
||||
void *tbl_ptr;
|
||||
int ret;
|
||||
|
||||
ret = qcom_scm_clk_enable();
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
ret = qcom_scm_bw_enable();
|
||||
if (ret)
|
||||
goto disable_clk;
|
||||
|
||||
/*
|
||||
* TrustZone can not accept buffer as NULL value as argument hence,
|
||||
* we need to pass a input buffer indicating that subsystem firmware
|
||||
* does not have resource table by filling resource table structure.
|
||||
*/
|
||||
if (!input_rt) {
|
||||
input_rt = &empty_rsc;
|
||||
input_rt_size = sizeof(empty_rsc);
|
||||
}
|
||||
|
||||
input_rt_tzm = qcom_tzmem_alloc(__scm->mempool, input_rt_size, GFP_KERNEL);
|
||||
if (!input_rt_tzm) {
|
||||
ret = -ENOMEM;
|
||||
goto disable_scm_bw;
|
||||
}
|
||||
|
||||
memcpy(input_rt_tzm, input_rt, input_rt_size);
|
||||
|
||||
output_rt_tzm = __qcom_scm_pas_get_rsc_table(ctx->pas_id, input_rt_tzm,
|
||||
input_rt_size, &size);
|
||||
if (PTR_ERR(output_rt_tzm) == -EOVERFLOW)
|
||||
/* Try again with the size requested by the TZ */
|
||||
output_rt_tzm = __qcom_scm_pas_get_rsc_table(ctx->pas_id,
|
||||
input_rt_tzm,
|
||||
input_rt_size,
|
||||
&size);
|
||||
if (IS_ERR(output_rt_tzm)) {
|
||||
ret = PTR_ERR(output_rt_tzm);
|
||||
goto free_input_rt;
|
||||
}
|
||||
|
||||
tbl_ptr = kzalloc(size, GFP_KERNEL);
|
||||
if (!tbl_ptr) {
|
||||
qcom_tzmem_free(output_rt_tzm);
|
||||
ret = -ENOMEM;
|
||||
goto free_input_rt;
|
||||
}
|
||||
|
||||
memcpy(tbl_ptr, output_rt_tzm, size);
|
||||
*output_rt_size = size;
|
||||
qcom_tzmem_free(output_rt_tzm);
|
||||
|
||||
free_input_rt:
|
||||
qcom_tzmem_free(input_rt_tzm);
|
||||
|
||||
disable_scm_bw:
|
||||
qcom_scm_bw_disable();
|
||||
|
||||
disable_clk:
|
||||
qcom_scm_clk_disable();
|
||||
|
||||
return ret ? ERR_PTR(ret) : tbl_ptr;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table);
|
||||
|
||||
/**
|
||||
* qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
|
||||
* and reset the remote processor
|
||||
* @peripheral: peripheral id
|
||||
* @pas_id: peripheral authentication service id
|
||||
*
|
||||
* Return 0 on success.
|
||||
*/
|
||||
int qcom_scm_pas_auth_and_reset(u32 peripheral)
|
||||
int qcom_scm_pas_auth_and_reset(u32 pas_id)
|
||||
{
|
||||
int ret;
|
||||
struct qcom_scm_desc desc = {
|
||||
.svc = QCOM_SCM_SVC_PIL,
|
||||
.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
|
||||
.arginfo = QCOM_SCM_ARGS(1),
|
||||
.args[0] = peripheral,
|
||||
.args[0] = pas_id,
|
||||
.owner = ARM_SMCCC_OWNER_SIP,
|
||||
};
|
||||
struct qcom_scm_res res;
|
||||
|
|
@ -743,20 +984,67 @@ disable_clk:
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset);
|
||||
|
||||
/**
|
||||
* qcom_scm_pas_prepare_and_auth_reset() - Prepare, authenticate, and reset the
|
||||
* remote processor
|
||||
*
|
||||
* @ctx: Context saved during call to qcom_scm_pas_context_init()
|
||||
*
|
||||
* This function performs the necessary steps to prepare a PAS subsystem,
|
||||
* authenticate it using the provided metadata, and initiate a reset sequence.
|
||||
*
|
||||
* It should be used when Linux is in control setting up the IOMMU hardware
|
||||
* for remote subsystem during secure firmware loading processes. The preparation
|
||||
* step sets up a shmbridge over the firmware memory before TrustZone accesses the
|
||||
* firmware memory region for authentication. The authentication step verifies
|
||||
* the integrity and authenticity of the firmware or configuration using secure
|
||||
* metadata. Finally, the reset step ensures the subsystem starts in a clean and
|
||||
* sane state.
|
||||
*
|
||||
* Return: 0 on success, negative errno on failure.
|
||||
*/
|
||||
int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx)
|
||||
{
|
||||
u64 handle;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* When Linux running @ EL1, Gunyah hypervisor running @ EL2 traps the
|
||||
* auth_and_reset call and create an shmbridge on the remote subsystem
|
||||
* memory region and then invokes a call to TrustZone to authenticate.
|
||||
*/
|
||||
if (!ctx->use_tzmem)
|
||||
return qcom_scm_pas_auth_and_reset(ctx->pas_id);
|
||||
|
||||
/*
|
||||
* When Linux runs @ EL2 Linux must create the shmbridge itself and then
|
||||
* subsequently call TrustZone for authenticate and reset.
|
||||
*/
|
||||
ret = qcom_tzmem_shm_bridge_create(ctx->mem_phys, ctx->mem_size, &handle);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_scm_pas_auth_and_reset(ctx->pas_id);
|
||||
qcom_tzmem_shm_bridge_delete(handle);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset);
|
||||
|
||||
/**
|
||||
* qcom_scm_pas_shutdown() - Shut down the remote processor
|
||||
* @peripheral: peripheral id
|
||||
* @pas_id: peripheral authentication service id
|
||||
*
|
||||
* Returns 0 on success.
|
||||
*/
|
||||
int qcom_scm_pas_shutdown(u32 peripheral)
|
||||
int qcom_scm_pas_shutdown(u32 pas_id)
|
||||
{
|
||||
int ret;
|
||||
struct qcom_scm_desc desc = {
|
||||
.svc = QCOM_SCM_SVC_PIL,
|
||||
.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
|
||||
.arginfo = QCOM_SCM_ARGS(1),
|
||||
.args[0] = peripheral,
|
||||
.args[0] = pas_id,
|
||||
.owner = ARM_SMCCC_OWNER_SIP,
|
||||
};
|
||||
struct qcom_scm_res res;
|
||||
|
|
@ -782,18 +1070,18 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown);
|
|||
/**
|
||||
* qcom_scm_pas_supported() - Check if the peripheral authentication service is
|
||||
* available for the given peripherial
|
||||
* @peripheral: peripheral id
|
||||
* @pas_id: peripheral authentication service id
|
||||
*
|
||||
* Returns true if PAS is supported for this peripheral, otherwise false.
|
||||
*/
|
||||
bool qcom_scm_pas_supported(u32 peripheral)
|
||||
bool qcom_scm_pas_supported(u32 pas_id)
|
||||
{
|
||||
int ret;
|
||||
struct qcom_scm_desc desc = {
|
||||
.svc = QCOM_SCM_SVC_PIL,
|
||||
.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
|
||||
.arginfo = QCOM_SCM_ARGS(1),
|
||||
.args[0] = peripheral,
|
||||
.args[0] = pas_id,
|
||||
.owner = ARM_SMCCC_OWNER_SIP,
|
||||
};
|
||||
struct qcom_scm_res res;
|
||||
|
|
|
|||
|
|
@ -105,6 +105,7 @@ int qcom_scm_shm_bridge_enable(struct device *scm_dev);
|
|||
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
|
||||
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
|
||||
#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
|
||||
#define QCOM_SCM_PIL_PAS_GET_RSCTABLE 0x21
|
||||
|
||||
#define QCOM_SCM_SVC_IO 0x05
|
||||
#define QCOM_SCM_IO_READ 0x01
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/iommu.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
|
|
@ -117,8 +118,8 @@ struct qcom_pas {
|
|||
struct qcom_rproc_ssr ssr_subdev;
|
||||
struct qcom_sysmon *sysmon;
|
||||
|
||||
struct qcom_scm_pas_metadata pas_metadata;
|
||||
struct qcom_scm_pas_metadata dtb_pas_metadata;
|
||||
struct qcom_scm_pas_context *pas_ctx;
|
||||
struct qcom_scm_pas_context *dtb_pas_ctx;
|
||||
};
|
||||
|
||||
static void qcom_pas_segment_dump(struct rproc *rproc,
|
||||
|
|
@ -211,9 +212,9 @@ static int qcom_pas_unprepare(struct rproc *rproc)
|
|||
* auth_and_reset() was successful, but in other cases clean it up
|
||||
* here.
|
||||
*/
|
||||
qcom_scm_pas_metadata_release(&pas->pas_metadata);
|
||||
qcom_scm_pas_metadata_release(pas->pas_ctx);
|
||||
if (pas->dtb_pas_id)
|
||||
qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata);
|
||||
qcom_scm_pas_metadata_release(pas->dtb_pas_ctx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -239,15 +240,9 @@ static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = qcom_mdt_pas_init(pas->dev, pas->dtb_firmware, pas->dtb_firmware_name,
|
||||
pas->dtb_pas_id, pas->dtb_mem_phys,
|
||||
&pas->dtb_pas_metadata);
|
||||
if (ret)
|
||||
goto release_dtb_firmware;
|
||||
|
||||
ret = qcom_mdt_load_no_init(pas->dev, pas->dtb_firmware, pas->dtb_firmware_name,
|
||||
pas->dtb_mem_region, pas->dtb_mem_phys,
|
||||
pas->dtb_mem_size, &pas->dtb_mem_reloc);
|
||||
ret = qcom_mdt_pas_load(pas->dtb_pas_ctx, pas->dtb_firmware,
|
||||
pas->dtb_firmware_name, pas->dtb_mem_region,
|
||||
&pas->dtb_mem_reloc);
|
||||
if (ret)
|
||||
goto release_dtb_metadata;
|
||||
}
|
||||
|
|
@ -255,14 +250,28 @@ static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw)
|
|||
return 0;
|
||||
|
||||
release_dtb_metadata:
|
||||
qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata);
|
||||
|
||||
release_dtb_firmware:
|
||||
qcom_scm_pas_metadata_release(pas->dtb_pas_ctx);
|
||||
release_firmware(pas->dtb_firmware);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void qcom_pas_unmap_carveout(struct rproc *rproc, phys_addr_t mem_phys, size_t size)
|
||||
{
|
||||
if (rproc->has_iommu)
|
||||
iommu_unmap(rproc->domain, mem_phys, size);
|
||||
}
|
||||
|
||||
static int qcom_pas_map_carveout(struct rproc *rproc, phys_addr_t mem_phys, size_t size)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (rproc->has_iommu)
|
||||
ret = iommu_map(rproc->domain, mem_phys, mem_phys, size,
|
||||
IOMMU_READ | IOMMU_WRITE, GFP_KERNEL);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qcom_pas_start(struct rproc *rproc)
|
||||
{
|
||||
struct qcom_pas *pas = rproc->priv;
|
||||
|
|
@ -297,54 +306,62 @@ static int qcom_pas_start(struct rproc *rproc)
|
|||
}
|
||||
|
||||
if (pas->dtb_pas_id) {
|
||||
ret = qcom_scm_pas_auth_and_reset(pas->dtb_pas_id);
|
||||
ret = qcom_pas_map_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
|
||||
if (ret)
|
||||
goto disable_px_supply;
|
||||
|
||||
ret = qcom_scm_pas_prepare_and_auth_reset(pas->dtb_pas_ctx);
|
||||
if (ret) {
|
||||
dev_err(pas->dev,
|
||||
"failed to authenticate dtb image and release reset\n");
|
||||
goto disable_px_supply;
|
||||
goto unmap_dtb_carveout;
|
||||
}
|
||||
}
|
||||
|
||||
ret = qcom_mdt_pas_init(pas->dev, pas->firmware, rproc->firmware, pas->pas_id,
|
||||
pas->mem_phys, &pas->pas_metadata);
|
||||
if (ret)
|
||||
goto disable_px_supply;
|
||||
|
||||
ret = qcom_mdt_load_no_init(pas->dev, pas->firmware, rproc->firmware,
|
||||
pas->mem_region, pas->mem_phys, pas->mem_size,
|
||||
&pas->mem_reloc);
|
||||
ret = qcom_mdt_pas_load(pas->pas_ctx, pas->firmware, rproc->firmware,
|
||||
pas->mem_region, &pas->mem_reloc);
|
||||
if (ret)
|
||||
goto release_pas_metadata;
|
||||
|
||||
qcom_pil_info_store(pas->info_name, pas->mem_phys, pas->mem_size);
|
||||
|
||||
ret = qcom_scm_pas_auth_and_reset(pas->pas_id);
|
||||
ret = qcom_pas_map_carveout(rproc, pas->mem_phys, pas->mem_size);
|
||||
if (ret)
|
||||
goto release_pas_metadata;
|
||||
|
||||
ret = qcom_scm_pas_prepare_and_auth_reset(pas->pas_ctx);
|
||||
if (ret) {
|
||||
dev_err(pas->dev,
|
||||
"failed to authenticate image and release reset\n");
|
||||
goto release_pas_metadata;
|
||||
goto unmap_carveout;
|
||||
}
|
||||
|
||||
ret = qcom_q6v5_wait_for_start(&pas->q6v5, msecs_to_jiffies(5000));
|
||||
if (ret == -ETIMEDOUT) {
|
||||
dev_err(pas->dev, "start timed out\n");
|
||||
qcom_scm_pas_shutdown(pas->pas_id);
|
||||
goto release_pas_metadata;
|
||||
goto unmap_carveout;
|
||||
}
|
||||
|
||||
qcom_scm_pas_metadata_release(&pas->pas_metadata);
|
||||
qcom_scm_pas_metadata_release(pas->pas_ctx);
|
||||
if (pas->dtb_pas_id)
|
||||
qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata);
|
||||
qcom_scm_pas_metadata_release(pas->dtb_pas_ctx);
|
||||
|
||||
/* firmware is used to pass reference from qcom_pas_start(), drop it now */
|
||||
pas->firmware = NULL;
|
||||
|
||||
return 0;
|
||||
|
||||
unmap_carveout:
|
||||
qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size);
|
||||
release_pas_metadata:
|
||||
qcom_scm_pas_metadata_release(&pas->pas_metadata);
|
||||
qcom_scm_pas_metadata_release(pas->pas_ctx);
|
||||
if (pas->dtb_pas_id)
|
||||
qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata);
|
||||
qcom_scm_pas_metadata_release(pas->dtb_pas_ctx);
|
||||
|
||||
unmap_dtb_carveout:
|
||||
if (pas->dtb_pas_id)
|
||||
qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
|
||||
disable_px_supply:
|
||||
if (pas->px_supply)
|
||||
regulator_disable(pas->px_supply);
|
||||
|
|
@ -400,8 +417,12 @@ static int qcom_pas_stop(struct rproc *rproc)
|
|||
ret = qcom_scm_pas_shutdown(pas->dtb_pas_id);
|
||||
if (ret)
|
||||
dev_err(pas->dev, "failed to shutdown dtb: %d\n", ret);
|
||||
|
||||
qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
|
||||
}
|
||||
|
||||
qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size);
|
||||
|
||||
handover = qcom_q6v5_unprepare(&pas->q6v5);
|
||||
if (handover)
|
||||
qcom_pas_handover(&pas->q6v5);
|
||||
|
|
@ -427,6 +448,61 @@ static void *qcom_pas_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is
|
|||
return pas->mem_region + offset;
|
||||
}
|
||||
|
||||
static int qcom_pas_parse_firmware(struct rproc *rproc, const struct firmware *fw)
|
||||
{
|
||||
struct qcom_pas *pas = rproc->priv;
|
||||
struct resource_table *table = NULL;
|
||||
size_t output_rt_size;
|
||||
void *output_rt;
|
||||
size_t table_sz;
|
||||
int ret;
|
||||
|
||||
ret = qcom_register_dump_segments(rproc, fw);
|
||||
if (ret) {
|
||||
dev_err(pas->dev, "Error in registering dump segments\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!rproc->has_iommu)
|
||||
return 0;
|
||||
|
||||
ret = rproc_elf_load_rsc_table(rproc, fw);
|
||||
if (ret)
|
||||
dev_dbg(&rproc->dev, "Failed to load resource table from firmware\n");
|
||||
|
||||
table = rproc->table_ptr;
|
||||
table_sz = rproc->table_sz;
|
||||
|
||||
/*
|
||||
* The resources consumed by Qualcomm remote processors fall into two categories:
|
||||
* static (such as the memory carveouts for the rproc firmware) and dynamic (like
|
||||
* shared memory pools). Both are managed by a Qualcomm hypervisor (such as QHEE
|
||||
* or Gunyah), if one is present. Otherwise, a resource table must be retrieved
|
||||
* via an SCM call. That table will list all dynamic resources (if any) and possibly
|
||||
* the static ones. The static resources may also come from a resource table embedded
|
||||
* in the rproc firmware instead.
|
||||
*
|
||||
* Here, we call rproc_elf_load_rsc_table() to check firmware binary has resources
|
||||
* or not and if it is not having then we pass NULL and zero as input resource
|
||||
* table pointer and size respectively to the argument of qcom_scm_pas_get_rsc_table()
|
||||
* and this is even true for Qualcomm remote processor who does follow remoteproc
|
||||
* framework.
|
||||
*/
|
||||
output_rt = qcom_scm_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &output_rt_size);
|
||||
ret = IS_ERR(output_rt) ? PTR_ERR(output_rt) : 0;
|
||||
if (ret) {
|
||||
dev_err(pas->dev, "Error in getting resource table: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
kfree(rproc->cached_table);
|
||||
rproc->cached_table = output_rt;
|
||||
rproc->table_ptr = rproc->cached_table;
|
||||
rproc->table_sz = output_rt_size;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long qcom_pas_panic(struct rproc *rproc)
|
||||
{
|
||||
struct qcom_pas *pas = rproc->priv;
|
||||
|
|
@ -439,7 +515,7 @@ static const struct rproc_ops qcom_pas_ops = {
|
|||
.start = qcom_pas_start,
|
||||
.stop = qcom_pas_stop,
|
||||
.da_to_va = qcom_pas_da_to_va,
|
||||
.parse_fw = qcom_register_dump_segments,
|
||||
.parse_fw = qcom_pas_parse_firmware,
|
||||
.load = qcom_pas_load,
|
||||
.panic = qcom_pas_panic,
|
||||
};
|
||||
|
|
@ -449,7 +525,7 @@ static const struct rproc_ops qcom_pas_minidump_ops = {
|
|||
.start = qcom_pas_start,
|
||||
.stop = qcom_pas_stop,
|
||||
.da_to_va = qcom_pas_da_to_va,
|
||||
.parse_fw = qcom_register_dump_segments,
|
||||
.parse_fw = qcom_pas_parse_firmware,
|
||||
.load = qcom_pas_load,
|
||||
.panic = qcom_pas_panic,
|
||||
.coredump = qcom_pas_minidump,
|
||||
|
|
@ -697,6 +773,7 @@ static int qcom_pas_probe(struct platform_device *pdev)
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
rproc->has_iommu = of_property_present(pdev->dev.of_node, "iommus");
|
||||
rproc->auto_boot = desc->auto_boot;
|
||||
rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
|
||||
|
||||
|
|
@ -760,6 +837,24 @@ static int qcom_pas_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
qcom_add_ssr_subdev(rproc, &pas->ssr_subdev, desc->ssr_name);
|
||||
|
||||
pas->pas_ctx = devm_qcom_scm_pas_context_alloc(pas->dev, pas->pas_id,
|
||||
pas->mem_phys, pas->mem_size);
|
||||
if (IS_ERR(pas->pas_ctx)) {
|
||||
ret = PTR_ERR(pas->pas_ctx);
|
||||
goto remove_ssr_sysmon;
|
||||
}
|
||||
|
||||
pas->dtb_pas_ctx = devm_qcom_scm_pas_context_alloc(pas->dev, pas->dtb_pas_id,
|
||||
pas->dtb_mem_phys,
|
||||
pas->dtb_mem_size);
|
||||
if (IS_ERR(pas->dtb_pas_ctx)) {
|
||||
ret = PTR_ERR(pas->dtb_pas_ctx);
|
||||
goto remove_ssr_sysmon;
|
||||
}
|
||||
|
||||
pas->pas_ctx->use_tzmem = rproc->has_iommu;
|
||||
pas->dtb_pas_ctx->use_tzmem = rproc->has_iommu;
|
||||
ret = rproc_add(rproc);
|
||||
if (ret)
|
||||
goto remove_ssr_sysmon;
|
||||
|
|
|
|||
|
|
@ -227,20 +227,9 @@ void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata);
|
||||
|
||||
/**
|
||||
* qcom_mdt_pas_init() - initialize PAS region for firmware loading
|
||||
* @dev: device handle to associate resources with
|
||||
* @fw: firmware object for the mdt file
|
||||
* @fw_name: name of the firmware, for construction of segment file names
|
||||
* @pas_id: PAS identifier
|
||||
* @mem_phys: physical address of allocated memory region
|
||||
* @ctx: PAS metadata context, to be released by caller
|
||||
*
|
||||
* Returns 0 on success, negative errno otherwise.
|
||||
*/
|
||||
int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, phys_addr_t mem_phys,
|
||||
struct qcom_scm_pas_metadata *ctx)
|
||||
static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, phys_addr_t mem_phys,
|
||||
struct qcom_scm_pas_context *ctx)
|
||||
{
|
||||
const struct elf32_phdr *phdrs;
|
||||
const struct elf32_phdr *phdr;
|
||||
|
|
@ -302,7 +291,6 @@ int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
|
|||
out:
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_mdt_pas_init);
|
||||
|
||||
static bool qcom_mdt_bins_are_split(const struct firmware *fw)
|
||||
{
|
||||
|
|
@ -469,7 +457,7 @@ int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
|||
{
|
||||
int ret;
|
||||
|
||||
ret = qcom_mdt_pas_init(dev, fw, fw_name, pas_id, mem_phys, NULL);
|
||||
ret = __qcom_mdt_pas_init(dev, fw, fw_name, pas_id, mem_phys, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -478,5 +466,36 @@ int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_mdt_load);
|
||||
|
||||
/**
|
||||
* qcom_mdt_pas_load - Loads and authenticates the metadata of the firmware
|
||||
* (typically contained in the .mdt file), followed by loading the actual
|
||||
* firmware segments (e.g., .bXX files). Authentication of the segments done
|
||||
* by a separate call.
|
||||
*
|
||||
* The PAS context must be initialized using qcom_scm_pas_context_init()
|
||||
* prior to invoking this function.
|
||||
*
|
||||
* @ctx: Pointer to the PAS (Peripheral Authentication Service) context
|
||||
* @fw: Firmware object representing the .mdt file
|
||||
* @firmware: Name of the firmware used to construct segment file names
|
||||
* @mem_region: Memory region allocated for loading the firmware
|
||||
* @reloc_base: Physical address adjusted after relocation
|
||||
*
|
||||
* Return: 0 on success or a negative error code on failure.
|
||||
*/
|
||||
int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw,
|
||||
const char *firmware, void *mem_region, phys_addr_t *reloc_base)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = __qcom_mdt_pas_init(ctx->dev, fw, firmware, ctx->pas_id, ctx->mem_phys, ctx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return qcom_mdt_load_no_init(ctx->dev, fw, firmware, mem_region, ctx->mem_phys,
|
||||
ctx->mem_size, reloc_base);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_mdt_pas_load);
|
||||
|
||||
MODULE_DESCRIPTION("Firmware parser for Qualcomm MDT format");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -66,19 +66,33 @@ int qcom_scm_set_warm_boot_addr(void *entry);
|
|||
void qcom_scm_cpu_power_down(u32 flags);
|
||||
int qcom_scm_set_remote_state(u32 state, u32 id);
|
||||
|
||||
struct qcom_scm_pas_metadata {
|
||||
struct qcom_scm_pas_context {
|
||||
struct device *dev;
|
||||
u32 pas_id;
|
||||
phys_addr_t mem_phys;
|
||||
size_t mem_size;
|
||||
void *ptr;
|
||||
dma_addr_t phys;
|
||||
ssize_t size;
|
||||
bool use_tzmem;
|
||||
};
|
||||
|
||||
int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
|
||||
struct qcom_scm_pas_metadata *ctx);
|
||||
void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
|
||||
int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
|
||||
int qcom_scm_pas_auth_and_reset(u32 peripheral);
|
||||
int qcom_scm_pas_shutdown(u32 peripheral);
|
||||
bool qcom_scm_pas_supported(u32 peripheral);
|
||||
struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev,
|
||||
u32 pas_id,
|
||||
phys_addr_t mem_phys,
|
||||
size_t mem_size);
|
||||
int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
|
||||
struct qcom_scm_pas_context *ctx);
|
||||
void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx);
|
||||
int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size);
|
||||
int qcom_scm_pas_auth_and_reset(u32 pas_id);
|
||||
int qcom_scm_pas_shutdown(u32 pas_id);
|
||||
bool qcom_scm_pas_supported(u32 pas_id);
|
||||
struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx,
|
||||
void *input_rt, size_t input_rt_size,
|
||||
size_t *output_rt_size);
|
||||
|
||||
int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx);
|
||||
|
||||
int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
|
||||
int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
|
||||
|
|
|
|||
|
|
@ -10,19 +10,19 @@
|
|||
|
||||
struct device;
|
||||
struct firmware;
|
||||
struct qcom_scm_pas_metadata;
|
||||
struct qcom_scm_pas_context;
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
|
||||
|
||||
ssize_t qcom_mdt_get_size(const struct firmware *fw);
|
||||
int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, phys_addr_t mem_phys,
|
||||
struct qcom_scm_pas_metadata *pas_metadata_ctx);
|
||||
int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, void *mem_region,
|
||||
phys_addr_t mem_phys, size_t mem_size,
|
||||
phys_addr_t *reloc_base);
|
||||
|
||||
int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw,
|
||||
const char *firmware, void *mem_region, phys_addr_t *reloc_base);
|
||||
|
||||
int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, void *mem_region,
|
||||
phys_addr_t mem_phys, size_t mem_size,
|
||||
|
|
@ -37,13 +37,6 @@ static inline ssize_t qcom_mdt_get_size(const struct firmware *fw)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, phys_addr_t mem_phys,
|
||||
struct qcom_scm_pas_metadata *pas_metadata_ctx)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id,
|
||||
void *mem_region, phys_addr_t mem_phys,
|
||||
|
|
@ -52,6 +45,13 @@ static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx,
|
||||
const struct firmware *fw, const char *firmware,
|
||||
void *mem_region, phys_addr_t *reloc_base)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_load_no_init(struct device *dev,
|
||||
const struct firmware *fw,
|
||||
const char *fw_name, void *mem_region,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue