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crypto: xilinx - Add gcm(aes) support for AMD/Xilinx Versal device
Add gcm(aes) algorithm support for AMD/Xilinx Versal devices. Signed-off-by: Harsh Jain <h.jain@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Harsh Jain
Herbert Xu
parent
856f061925
commit
280bfc3eb5
1 changed files with 421 additions and 9 deletions
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@ -1,7 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx ZynqMP AES Driver.
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* Copyright (c) 2020 Xilinx Inc.
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* Copyright (C) 2020-2022 Xilinx Inc.
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* Copyright (C) 2022-2025 Advanced Micro Devices, Inc.
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*/
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#include <crypto/aes.h>
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@ -19,11 +20,13 @@
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#include <linux/string.h>
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#define ZYNQMP_DMA_BIT_MASK 32U
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#define VERSAL_DMA_BIT_MASK 64U
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#define XILINX_AES_AUTH_SIZE 16U
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#define XILINX_AES_BLK_SIZE 1U
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#define ZYNQMP_AES_MIN_INPUT_BLK_SIZE 4U
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#define ZYNQMP_AES_WORD_LEN 4U
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#define VERSAL_AES_QWORD_LEN 16U
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#define ZYNQMP_AES_GCM_TAG_MISMATCH_ERR 0x01
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#define ZYNQMP_AES_WRONG_KEY_SRC_ERR 0x13
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#define ZYNQMP_AES_PUF_NOT_PROGRAMMED 0xE300
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@ -49,6 +52,7 @@ struct xilinx_aead_dev {
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struct xilinx_aead_alg {
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struct xilinx_aead_dev *aead_dev;
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struct aead_engine_alg aead;
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int (*aes_aead_cipher)(struct aead_request *areq);
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u8 dma_bit_mask;
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};
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@ -83,6 +87,54 @@ struct xilinx_aead_req_ctx {
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static struct xilinx_aead_dev *aead_dev;
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enum versal_aead_keysrc {
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VERSAL_AES_BBRAM_KEY = 0,
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VERSAL_AES_BBRAM_RED_KEY,
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VERSAL_AES_BH_KEY,
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VERSAL_AES_BH_RED_KEY,
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VERSAL_AES_EFUSE_KEY,
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VERSAL_AES_EFUSE_RED_KEY,
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VERSAL_AES_EFUSE_USER_KEY_0,
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VERSAL_AES_EFUSE_USER_KEY_1,
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VERSAL_AES_EFUSE_USER_RED_KEY_0,
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VERSAL_AES_EFUSE_USER_RED_KEY_1,
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VERSAL_AES_KUP_KEY,
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VERSAL_AES_PUF_KEY,
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VERSAL_AES_USER_KEY_0,
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VERSAL_AES_USER_KEY_1,
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VERSAL_AES_USER_KEY_2,
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VERSAL_AES_USER_KEY_3,
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VERSAL_AES_USER_KEY_4,
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VERSAL_AES_USER_KEY_5,
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VERSAL_AES_USER_KEY_6,
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VERSAL_AES_USER_KEY_7,
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VERSAL_AES_EXPANDED_KEYS,
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VERSAL_AES_ALL_KEYS,
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};
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enum versal_aead_op {
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VERSAL_AES_ENCRYPT = 0,
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VERSAL_AES_DECRYPT
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};
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enum versal_aes_keysize {
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HW_AES_KEY_SIZE_128 = 0,
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HW_AES_KEY_SIZE_256 = 2,
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};
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struct versal_init_ops {
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u64 iv;
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u32 op;
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u32 keysrc;
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u32 size;
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};
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struct versal_in_params {
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u64 in_data_addr;
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u32 size;
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u32 is_last;
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};
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static int zynqmp_aes_aead_cipher(struct aead_request *req)
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{
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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@ -187,6 +239,141 @@ freemem:
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return ret;
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}
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static int versal_aes_aead_cipher(struct aead_request *req)
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{
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
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struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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dma_addr_t dma_addr_data, dma_addr_hw_req, dma_addr_in;
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u32 total_len = req->assoclen + req->cryptlen;
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struct device *dev = tfm_ctx->dev;
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struct versal_init_ops *hwreq;
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struct versal_in_params *in;
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u32 gcm_offset, out_len;
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size_t dmabuf_size;
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size_t kbuf_size;
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void *dmabuf;
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char *kbuf;
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int ret;
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kbuf_size = total_len + XILINX_AES_AUTH_SIZE;
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kbuf = kmalloc(kbuf_size, GFP_KERNEL);
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if (unlikely(!kbuf)) {
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ret = -ENOMEM;
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goto err;
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}
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dmabuf_size = sizeof(struct versal_init_ops) +
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sizeof(struct versal_in_params) +
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GCM_AES_IV_SIZE;
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dmabuf = kmalloc(dmabuf_size, GFP_KERNEL);
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if (unlikely(!dmabuf)) {
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ret = -ENOMEM;
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goto buf1_free;
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}
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dma_addr_hw_req = dma_map_single(dev, dmabuf, dmabuf_size, DMA_BIDIRECTIONAL);
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if (unlikely(dma_mapping_error(dev, dma_addr_hw_req))) {
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ret = -ENOMEM;
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goto buf2_free;
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}
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scatterwalk_map_and_copy(kbuf, req->src, 0, total_len, 0);
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dma_addr_data = dma_map_single(dev, kbuf, kbuf_size, DMA_BIDIRECTIONAL);
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if (unlikely(dma_mapping_error(dev, dma_addr_data))) {
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dma_unmap_single(dev, dma_addr_hw_req, dmabuf_size, DMA_BIDIRECTIONAL);
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ret = -ENOMEM;
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goto buf2_free;
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}
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hwreq = dmabuf;
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in = dmabuf + sizeof(struct versal_init_ops);
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memcpy(dmabuf + sizeof(struct versal_init_ops) +
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sizeof(struct versal_in_params), req->iv, GCM_AES_IV_SIZE);
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hwreq->iv = dma_addr_hw_req + sizeof(struct versal_init_ops) +
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sizeof(struct versal_in_params);
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hwreq->keysrc = tfm_ctx->keysrc;
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dma_addr_in = dma_addr_hw_req + sizeof(struct versal_init_ops);
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if (rq_ctx->op == XILINX_AES_ENCRYPT) {
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hwreq->op = VERSAL_AES_ENCRYPT;
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out_len = total_len + crypto_aead_authsize(aead);
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in->size = req->cryptlen;
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} else {
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hwreq->op = VERSAL_AES_DECRYPT;
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out_len = total_len - XILINX_AES_AUTH_SIZE;
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in->size = req->cryptlen - XILINX_AES_AUTH_SIZE;
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}
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if (tfm_ctx->keylen == AES_KEYSIZE_128)
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hwreq->size = HW_AES_KEY_SIZE_128;
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else
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hwreq->size = HW_AES_KEY_SIZE_256;
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/* Request aes key write for volatile user keys */
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if (hwreq->keysrc >= VERSAL_AES_USER_KEY_0 && hwreq->keysrc <= VERSAL_AES_USER_KEY_7) {
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ret = versal_pm_aes_key_write(hwreq->size, hwreq->keysrc,
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tfm_ctx->key_dma_addr);
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if (ret)
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goto unmap;
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}
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in->in_data_addr = dma_addr_data + req->assoclen;
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in->is_last = 1;
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gcm_offset = req->assoclen + in->size;
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dma_sync_single_for_device(dev, dma_addr_hw_req, dmabuf_size, DMA_BIDIRECTIONAL);
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ret = versal_pm_aes_op_init(dma_addr_hw_req);
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if (ret)
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goto clearkey;
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if (req->assoclen > 0) {
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/* Currently GMAC is OFF by default */
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ret = versal_pm_aes_update_aad(dma_addr_data, req->assoclen);
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if (ret)
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goto clearkey;
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}
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if (rq_ctx->op == XILINX_AES_ENCRYPT) {
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ret = versal_pm_aes_enc_update(dma_addr_in,
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dma_addr_data + req->assoclen);
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if (ret)
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goto clearkey;
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ret = versal_pm_aes_enc_final(dma_addr_data + gcm_offset);
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if (ret)
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goto clearkey;
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} else {
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ret = versal_pm_aes_dec_update(dma_addr_in,
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dma_addr_data + req->assoclen);
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if (ret)
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goto clearkey;
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ret = versal_pm_aes_dec_final(dma_addr_data + gcm_offset);
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if (ret) {
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ret = -EBADMSG;
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goto clearkey;
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}
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}
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dma_unmap_single(dev, dma_addr_data, kbuf_size, DMA_BIDIRECTIONAL);
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dma_unmap_single(dev, dma_addr_hw_req, dmabuf_size, DMA_BIDIRECTIONAL);
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sg_copy_from_buffer(req->dst, sg_nents(req->dst),
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kbuf, out_len);
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dma_addr_data = 0;
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dma_addr_hw_req = 0;
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clearkey:
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if (hwreq->keysrc >= VERSAL_AES_USER_KEY_0 && hwreq->keysrc <= VERSAL_AES_USER_KEY_7)
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versal_pm_aes_key_zero(hwreq->keysrc);
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unmap:
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if (unlikely(dma_addr_data))
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dma_unmap_single(dev, dma_addr_data, kbuf_size, DMA_BIDIRECTIONAL);
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if (unlikely(dma_addr_hw_req))
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dma_unmap_single(dev, dma_addr_hw_req, dmabuf_size, DMA_BIDIRECTIONAL);
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buf2_free:
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memzero_explicit(dmabuf, dmabuf_size);
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kfree(dmabuf);
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buf1_free:
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memzero_explicit(kbuf, kbuf_size);
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kfree(kbuf);
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err:
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return ret;
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}
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static int zynqmp_fallback_check(struct xilinx_aead_tfm_ctx *tfm_ctx,
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struct aead_request *req)
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{
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@ -212,13 +399,40 @@ static int zynqmp_fallback_check(struct xilinx_aead_tfm_ctx *tfm_ctx,
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return 0;
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}
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static int versal_fallback_check(struct xilinx_aead_tfm_ctx *tfm_ctx,
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struct aead_request *req)
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{
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struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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if (tfm_ctx->authsize != XILINX_AES_AUTH_SIZE && rq_ctx->op == XILINX_AES_DECRYPT)
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return 1;
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if (tfm_ctx->keylen == AES_KEYSIZE_192)
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return 1;
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if (req->cryptlen < ZYNQMP_AES_MIN_INPUT_BLK_SIZE ||
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req->cryptlen % ZYNQMP_AES_WORD_LEN ||
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req->assoclen % VERSAL_AES_QWORD_LEN)
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return 1;
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if (rq_ctx->op == XILINX_AES_DECRYPT &&
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req->cryptlen <= XILINX_AES_AUTH_SIZE)
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return 1;
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return 0;
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}
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static int xilinx_handle_aes_req(struct crypto_engine *engine, void *req)
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{
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struct aead_request *areq =
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container_of(req, struct aead_request, base);
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct aead_alg *alg = crypto_aead_alg(aead);
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struct xilinx_aead_alg *drv_ctx;
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int err;
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err = zynqmp_aes_aead_cipher(areq);
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drv_ctx = container_of(alg, struct xilinx_aead_alg, aead.base);
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err = drv_ctx->aes_aead_cipher(areq);
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local_bh_disable();
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crypto_finalize_aead_request(engine, areq, err);
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local_bh_enable();
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@ -278,6 +492,84 @@ static int zynqmp_paes_aead_setkey(struct crypto_aead *aead, const u8 *key,
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return err;
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}
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static int versal_aes_aead_setkey(struct crypto_aead *aead, const u8 *key,
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unsigned int keylen)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_tfm_ctx(tfm);
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struct xilinx_hwkey_info hwkey;
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unsigned char keysrc;
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int err;
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tfm_ctx->keysrc = VERSAL_AES_USER_KEY_0;
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if (keylen == sizeof(struct xilinx_hwkey_info)) {
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memcpy(&hwkey, key, sizeof(struct xilinx_hwkey_info));
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if (hwkey.magic != XILINX_KEY_MAGIC)
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return -EINVAL;
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keysrc = hwkey.type;
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if (keysrc >= VERSAL_AES_USER_KEY_1 &&
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keysrc <= VERSAL_AES_USER_KEY_7) {
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tfm_ctx->keysrc = keysrc;
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tfm_ctx->keylen = sizeof(struct xilinx_hwkey_info);
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return 0;
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}
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return -EINVAL;
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}
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if (keylen == AES_KEYSIZE_256 || keylen == AES_KEYSIZE_128) {
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tfm_ctx->keylen = keylen;
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memcpy(tfm_ctx->key, key, keylen);
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dma_sync_single_for_device(tfm_ctx->dev, tfm_ctx->key_dma_addr,
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AES_KEYSIZE_256,
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DMA_TO_DEVICE);
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}
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tfm_ctx->fbk_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
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tfm_ctx->fbk_cipher->base.crt_flags |= (aead->base.crt_flags &
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CRYPTO_TFM_REQ_MASK);
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err = crypto_aead_setkey(tfm_ctx->fbk_cipher, key, keylen);
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if (!err)
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tfm_ctx->keylen = keylen;
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return err;
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}
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static int versal_paes_aead_setkey(struct crypto_aead *aead, const u8 *key,
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unsigned int keylen)
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{
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struct crypto_tfm *tfm = crypto_aead_tfm(aead);
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struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_tfm_ctx(tfm);
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struct xilinx_hwkey_info hwkey;
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unsigned char keysrc;
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int err = 0;
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if (keylen != sizeof(struct xilinx_hwkey_info))
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return -EINVAL;
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memcpy(&hwkey, key, sizeof(struct xilinx_hwkey_info));
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if (hwkey.magic != XILINX_KEY_MAGIC)
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return -EINVAL;
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keysrc = hwkey.type;
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switch (keysrc) {
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case VERSAL_AES_EFUSE_USER_KEY_0:
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case VERSAL_AES_EFUSE_USER_KEY_1:
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case VERSAL_AES_EFUSE_USER_RED_KEY_0:
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case VERSAL_AES_EFUSE_USER_RED_KEY_1:
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case VERSAL_AES_PUF_KEY:
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tfm_ctx->keysrc = keysrc;
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tfm_ctx->keylen = sizeof(struct xilinx_hwkey_info);
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break;
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default:
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err = -EINVAL;
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break;
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}
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return err;
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}
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static int xilinx_aes_aead_setauthsize(struct crypto_aead *aead,
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unsigned int authsize)
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{
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@ -328,6 +620,31 @@ static int zynqmp_aes_aead_encrypt(struct aead_request *req)
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return crypto_transfer_aead_request_to_engine(drv_ctx->aead_dev->engine, req);
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}
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static int versal_aes_aead_encrypt(struct aead_request *req)
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{
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struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
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struct aead_alg *alg = crypto_aead_alg(aead);
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struct xilinx_aead_alg *drv_ctx;
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int err;
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drv_ctx = container_of(alg, struct xilinx_aead_alg, aead.base);
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rq_ctx->op = XILINX_AES_ENCRYPT;
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if (tfm_ctx->keysrc >= VERSAL_AES_USER_KEY_0 &&
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tfm_ctx->keysrc <= VERSAL_AES_USER_KEY_7 &&
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tfm_ctx->keylen == sizeof(struct xilinx_hwkey_info))
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return -EINVAL;
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err = versal_fallback_check(tfm_ctx, req);
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if (err && (tfm_ctx->keysrc < VERSAL_AES_USER_KEY_0 ||
|
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tfm_ctx->keysrc > VERSAL_AES_USER_KEY_7))
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return -EOPNOTSUPP;
|
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if (err)
|
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return xilinx_aes_fallback_crypt(req, true);
|
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|
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return crypto_transfer_aead_request_to_engine(drv_ctx->aead_dev->engine, req);
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}
|
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|
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static int zynqmp_aes_aead_decrypt(struct aead_request *req)
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{
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struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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|
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@ -368,6 +685,33 @@ static int xilinx_paes_aead_init(struct crypto_aead *aead)
|
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return 0;
|
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}
|
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|
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static int versal_aes_aead_decrypt(struct aead_request *req)
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{
|
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struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
|
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
|
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struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
|
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struct aead_alg *alg = crypto_aead_alg(aead);
|
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struct xilinx_aead_alg *drv_ctx;
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int err;
|
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|
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drv_ctx = container_of(alg, struct xilinx_aead_alg, aead.base);
|
||||
rq_ctx->op = XILINX_AES_DECRYPT;
|
||||
if (tfm_ctx->keysrc >= VERSAL_AES_USER_KEY_0 &&
|
||||
tfm_ctx->keysrc <= VERSAL_AES_USER_KEY_7 &&
|
||||
tfm_ctx->keylen == sizeof(struct xilinx_hwkey_info))
|
||||
return -EINVAL;
|
||||
|
||||
err = versal_fallback_check(tfm_ctx, req);
|
||||
if (err &&
|
||||
(tfm_ctx->keysrc < VERSAL_AES_USER_KEY_0 ||
|
||||
tfm_ctx->keysrc > VERSAL_AES_USER_KEY_7))
|
||||
return -EOPNOTSUPP;
|
||||
if (err)
|
||||
return xilinx_aes_fallback_crypt(req, false);
|
||||
|
||||
return crypto_transfer_aead_request_to_engine(drv_ctx->aead_dev->engine, req);
|
||||
}
|
||||
|
||||
static int xilinx_aes_aead_init(struct crypto_aead *aead)
|
||||
{
|
||||
struct crypto_tfm *tfm = crypto_aead_tfm(aead);
|
||||
|
|
@ -384,8 +728,8 @@ static int xilinx_aes_aead_init(struct crypto_aead *aead)
|
|||
CRYPTO_ALG_NEED_FALLBACK);
|
||||
|
||||
if (IS_ERR(tfm_ctx->fbk_cipher)) {
|
||||
pr_err("%s() Error: failed to allocate fallback for %s\n",
|
||||
__func__, drv_ctx->aead.base.base.cra_name);
|
||||
dev_err(tfm_ctx->dev, "failed to allocate fallback for %s\n",
|
||||
drv_ctx->aead.base.base.cra_name);
|
||||
return PTR_ERR(tfm_ctx->fbk_cipher);
|
||||
}
|
||||
tfm_ctx->key = kmalloc(AES_KEYSIZE_256, GFP_KERNEL);
|
||||
|
|
@ -433,6 +777,7 @@ static void xilinx_aes_aead_exit(struct crypto_aead *aead)
|
|||
|
||||
static struct xilinx_aead_alg zynqmp_aes_algs[] = {
|
||||
{
|
||||
.aes_aead_cipher = zynqmp_aes_aead_cipher,
|
||||
.aead.base = {
|
||||
.setkey = zynqmp_aes_aead_setkey,
|
||||
.setauthsize = xilinx_aes_aead_setauthsize,
|
||||
|
|
@ -462,6 +807,7 @@ static struct xilinx_aead_alg zynqmp_aes_algs[] = {
|
|||
.dma_bit_mask = ZYNQMP_DMA_BIT_MASK,
|
||||
},
|
||||
{
|
||||
.aes_aead_cipher = zynqmp_aes_aead_cipher,
|
||||
.aead.base = {
|
||||
.setkey = zynqmp_paes_aead_setkey,
|
||||
.setauthsize = xilinx_aes_aead_setauthsize,
|
||||
|
|
@ -492,12 +838,80 @@ static struct xilinx_aead_alg zynqmp_aes_algs[] = {
|
|||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct xilinx_aead_alg versal_aes_algs[] = {
|
||||
{
|
||||
.aes_aead_cipher = versal_aes_aead_cipher,
|
||||
.aead.base = {
|
||||
.setkey = versal_aes_aead_setkey,
|
||||
.setauthsize = xilinx_aes_aead_setauthsize,
|
||||
.encrypt = versal_aes_aead_encrypt,
|
||||
.decrypt = versal_aes_aead_decrypt,
|
||||
.init = xilinx_aes_aead_init,
|
||||
.exit = xilinx_aes_aead_exit,
|
||||
.ivsize = GCM_AES_IV_SIZE,
|
||||
.maxauthsize = XILINX_AES_AUTH_SIZE,
|
||||
.base = {
|
||||
.cra_name = "gcm(aes)",
|
||||
.cra_driver_name = "versal-aes-gcm",
|
||||
.cra_priority = 300,
|
||||
.cra_flags = CRYPTO_ALG_TYPE_AEAD |
|
||||
CRYPTO_ALG_ASYNC |
|
||||
CRYPTO_ALG_ALLOCATES_MEMORY |
|
||||
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
||||
CRYPTO_ALG_NEED_FALLBACK,
|
||||
.cra_blocksize = XILINX_AES_BLK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct xilinx_aead_tfm_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
}
|
||||
},
|
||||
.aead.op = {
|
||||
.do_one_request = xilinx_handle_aes_req,
|
||||
},
|
||||
.dma_bit_mask = VERSAL_DMA_BIT_MASK,
|
||||
},
|
||||
{
|
||||
.aes_aead_cipher = versal_aes_aead_cipher,
|
||||
.aead.base = {
|
||||
.setkey = versal_paes_aead_setkey,
|
||||
.setauthsize = xilinx_aes_aead_setauthsize,
|
||||
.encrypt = versal_aes_aead_encrypt,
|
||||
.decrypt = versal_aes_aead_decrypt,
|
||||
.init = xilinx_paes_aead_init,
|
||||
.exit = xilinx_paes_aead_exit,
|
||||
.ivsize = GCM_AES_IV_SIZE,
|
||||
.maxauthsize = XILINX_AES_AUTH_SIZE,
|
||||
.base = {
|
||||
.cra_name = "gcm(paes)",
|
||||
.cra_driver_name = "versal-paes-gcm",
|
||||
.cra_priority = 300,
|
||||
.cra_flags = CRYPTO_ALG_TYPE_AEAD |
|
||||
CRYPTO_ALG_ASYNC |
|
||||
CRYPTO_ALG_ALLOCATES_MEMORY |
|
||||
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
||||
.cra_blocksize = XILINX_AES_BLK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct xilinx_aead_tfm_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
}
|
||||
},
|
||||
.aead.op = {
|
||||
.do_one_request = xilinx_handle_aes_req,
|
||||
},
|
||||
.dma_bit_mask = VERSAL_DMA_BIT_MASK,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct xlnx_feature aes_feature_map[] = {
|
||||
{
|
||||
.family = PM_ZYNQMP_FAMILY_CODE,
|
||||
.feature_id = PM_SECURE_AES,
|
||||
.data = zynqmp_aes_algs,
|
||||
},
|
||||
{
|
||||
.family = PM_VERSAL_FAMILY_CODE,
|
||||
.feature_id = XSECURE_API_AES_OP_INIT,
|
||||
.data = versal_aes_algs,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
@ -534,14 +948,13 @@ static int xilinx_aes_aead_probe(struct platform_device *pdev)
|
|||
aead_dev->engine = crypto_engine_alloc_init(dev, 1);
|
||||
if (!aead_dev->engine) {
|
||||
dev_err(dev, "Cannot alloc AES engine\n");
|
||||
err = -ENOMEM;
|
||||
goto err_engine;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
err = crypto_engine_start(aead_dev->engine);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot start AES engine\n");
|
||||
goto err_engine;
|
||||
goto err_engine_start;
|
||||
}
|
||||
|
||||
for (i = 0; aead_dev->aead_algs[i].dma_bit_mask; i++) {
|
||||
|
|
@ -552,14 +965,13 @@ static int xilinx_aes_aead_probe(struct platform_device *pdev)
|
|||
goto err_alg_register;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
|
||||
err_alg_register:
|
||||
while (i > 0)
|
||||
crypto_engine_unregister_aead(&aead_dev->aead_algs[--i].aead);
|
||||
err_engine:
|
||||
err_engine_start:
|
||||
crypto_engine_exit(aead_dev->engine);
|
||||
|
||||
return err;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue