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tools headers: Import asm-generic MMIO helpers
Import the asm-generic MMIO helper functions from the kernel headers into tools/include/. The top-level include is <linux/io.h> which then includes the arch-specific <asm/io.h>, which then includes <asm-generic/io.h>. This layout is chosen to match the kernel header layout and to appease checkpatch.pl (which warns against including <asm/io.h> or <asm-generic/io.h> directly). Changes made when importing: - Add missing includes at the top. - Stub out mmiowb_set_pending(). - Stub out _THIS_IP_. - Stub out log_*_mmio() calls. - Drop the CONFIG_64BIT checks, since tools/include/linux/types.h always defines u64. Acked-by: Shuah Khan <skhan@linuxfoundation.org> Signed-off-by: David Matlack <dmatlack@google.com> Link: https://lore.kernel.org/r/20250822212518.4156428-16-dmatlack@google.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
This commit is contained in:
David Matlack
Alex Williamson
parent
9bf9b185e3
commit
1f9c8edd6a
3 changed files with 492 additions and 1 deletions
482
tools/include/asm-generic/io.h
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482
tools/include/asm-generic/io.h
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _TOOLS_ASM_GENERIC_IO_H
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#define _TOOLS_ASM_GENERIC_IO_H
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#include <asm/barrier.h>
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#include <asm/byteorder.h>
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#ifndef mmiowb_set_pending
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#define mmiowb_set_pending() do { } while (0)
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#endif
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#ifndef __io_br
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#define __io_br() barrier()
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#endif
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/* prevent prefetching of coherent DMA data ahead of a dma-complete */
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#ifndef __io_ar
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#ifdef rmb
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#define __io_ar(v) rmb()
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#else
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#define __io_ar(v) barrier()
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#endif
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#endif
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/* flush writes to coherent DMA data before possibly triggering a DMA read */
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#ifndef __io_bw
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#ifdef wmb
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#define __io_bw() wmb()
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#else
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#define __io_bw() barrier()
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#endif
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#endif
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/* serialize device access against a spin_unlock, usually handled there. */
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#ifndef __io_aw
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#define __io_aw() mmiowb_set_pending()
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#endif
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#ifndef __io_pbw
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#define __io_pbw() __io_bw()
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#endif
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#ifndef __io_paw
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#define __io_paw() __io_aw()
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#endif
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#ifndef __io_pbr
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#define __io_pbr() __io_br()
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#endif
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#ifndef __io_par
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#define __io_par(v) __io_ar(v)
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#endif
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#ifndef _THIS_IP_
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#define _THIS_IP_ 0
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#endif
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static inline void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
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unsigned long caller_addr, unsigned long caller_addr0) {}
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static inline void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
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unsigned long caller_addr, unsigned long caller_addr0) {}
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static inline void log_read_mmio(u8 width, const volatile void __iomem *addr,
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unsigned long caller_addr, unsigned long caller_addr0) {}
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static inline void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
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unsigned long caller_addr, unsigned long caller_addr0) {}
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/*
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* __raw_{read,write}{b,w,l,q}() access memory in native endianness.
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*
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* On some architectures memory mapped IO needs to be accessed differently.
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* On the simple architectures, we just read/write the memory location
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* directly.
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*/
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#ifndef __raw_readb
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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return *(const volatile u8 __force *)addr;
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}
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#endif
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#ifndef __raw_readw
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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return *(const volatile u16 __force *)addr;
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}
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#endif
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#ifndef __raw_readl
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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return *(const volatile u32 __force *)addr;
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}
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#endif
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#ifndef __raw_readq
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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return *(const volatile u64 __force *)addr;
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}
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#endif
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#ifndef __raw_writeb
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
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{
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*(volatile u8 __force *)addr = value;
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}
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#endif
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#ifndef __raw_writew
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 value, volatile void __iomem *addr)
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{
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*(volatile u16 __force *)addr = value;
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}
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#endif
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#ifndef __raw_writel
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 value, volatile void __iomem *addr)
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{
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*(volatile u32 __force *)addr = value;
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}
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#endif
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#ifndef __raw_writeq
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
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{
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*(volatile u64 __force *)addr = value;
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}
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#endif
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/*
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* {read,write}{b,w,l,q}() access little endian memory and return result in
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* native endianness.
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*/
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#ifndef readb
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#define readb readb
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static inline u8 readb(const volatile void __iomem *addr)
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{
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u8 val;
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log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
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__io_br();
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val = __raw_readb(addr);
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__io_ar(val);
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log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);
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return val;
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}
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#endif
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#ifndef readw
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#define readw readw
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static inline u16 readw(const volatile void __iomem *addr)
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{
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u16 val;
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log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
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__io_br();
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val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
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__io_ar(val);
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log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);
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return val;
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}
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#endif
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#ifndef readl
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#define readl readl
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static inline u32 readl(const volatile void __iomem *addr)
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{
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u32 val;
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log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
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__io_br();
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val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
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__io_ar(val);
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log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);
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return val;
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}
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#endif
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#ifndef readq
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#define readq readq
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static inline u64 readq(const volatile void __iomem *addr)
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{
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u64 val;
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log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
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__io_br();
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val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
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__io_ar(val);
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log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);
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return val;
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}
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#endif
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#ifndef writeb
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#define writeb writeb
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static inline void writeb(u8 value, volatile void __iomem *addr)
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{
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log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
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__io_bw();
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__raw_writeb(value, addr);
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__io_aw();
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log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
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}
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#endif
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#ifndef writew
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#define writew writew
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static inline void writew(u16 value, volatile void __iomem *addr)
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{
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log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
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__io_bw();
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__raw_writew((u16 __force)cpu_to_le16(value), addr);
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__io_aw();
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log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
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}
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#endif
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#ifndef writel
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#define writel writel
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static inline void writel(u32 value, volatile void __iomem *addr)
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{
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log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
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__io_bw();
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__raw_writel((u32 __force)__cpu_to_le32(value), addr);
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__io_aw();
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log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
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}
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#endif
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#ifndef writeq
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#define writeq writeq
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static inline void writeq(u64 value, volatile void __iomem *addr)
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{
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log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
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__io_bw();
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__raw_writeq((u64 __force)__cpu_to_le64(value), addr);
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__io_aw();
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log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
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}
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#endif
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/*
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* {read,write}{b,w,l,q}_relaxed() are like the regular version, but
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* are not guaranteed to provide ordering against spinlocks or memory
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* accesses.
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*/
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#ifndef readb_relaxed
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#define readb_relaxed readb_relaxed
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static inline u8 readb_relaxed(const volatile void __iomem *addr)
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{
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u8 val;
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log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
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val = __raw_readb(addr);
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log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);
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return val;
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}
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#endif
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#ifndef readw_relaxed
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#define readw_relaxed readw_relaxed
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static inline u16 readw_relaxed(const volatile void __iomem *addr)
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{
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u16 val;
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log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
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val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
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log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);
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return val;
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}
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#endif
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#ifndef readl_relaxed
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#define readl_relaxed readl_relaxed
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static inline u32 readl_relaxed(const volatile void __iomem *addr)
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{
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u32 val;
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log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
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val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
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log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);
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return val;
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}
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#endif
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#if defined(readq) && !defined(readq_relaxed)
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#define readq_relaxed readq_relaxed
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static inline u64 readq_relaxed(const volatile void __iomem *addr)
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{
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u64 val;
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log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
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val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
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log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);
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return val;
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}
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#endif
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#ifndef writeb_relaxed
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#define writeb_relaxed writeb_relaxed
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static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
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{
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log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
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__raw_writeb(value, addr);
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log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
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}
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#endif
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#ifndef writew_relaxed
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#define writew_relaxed writew_relaxed
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static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
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{
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log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
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__raw_writew((u16 __force)cpu_to_le16(value), addr);
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log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
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}
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#endif
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#ifndef writel_relaxed
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#define writel_relaxed writel_relaxed
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static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
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{
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log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
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__raw_writel((u32 __force)__cpu_to_le32(value), addr);
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log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
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}
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#endif
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#if defined(writeq) && !defined(writeq_relaxed)
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#define writeq_relaxed writeq_relaxed
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static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)
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{
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log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
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__raw_writeq((u64 __force)__cpu_to_le64(value), addr);
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log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
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}
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#endif
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/*
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* {read,write}s{b,w,l,q}() repeatedly access the same memory address in
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* native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
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*/
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#ifndef readsb
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#define readsb readsb
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static inline void readsb(const volatile void __iomem *addr, void *buffer,
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unsigned int count)
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{
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if (count) {
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u8 *buf = buffer;
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do {
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u8 x = __raw_readb(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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#endif
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#ifndef readsw
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#define readsw readsw
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static inline void readsw(const volatile void __iomem *addr, void *buffer,
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unsigned int count)
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{
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if (count) {
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u16 *buf = buffer;
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do {
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u16 x = __raw_readw(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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#endif
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#ifndef readsl
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#define readsl readsl
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static inline void readsl(const volatile void __iomem *addr, void *buffer,
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unsigned int count)
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{
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if (count) {
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u32 *buf = buffer;
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do {
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u32 x = __raw_readl(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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#endif
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#ifndef readsq
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#define readsq readsq
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static inline void readsq(const volatile void __iomem *addr, void *buffer,
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unsigned int count)
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{
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if (count) {
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u64 *buf = buffer;
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do {
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u64 x = __raw_readq(addr);
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*buf++ = x;
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} while (--count);
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}
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}
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#endif
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#ifndef writesb
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#define writesb writesb
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static inline void writesb(volatile void __iomem *addr, const void *buffer,
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unsigned int count)
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{
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if (count) {
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const u8 *buf = buffer;
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do {
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__raw_writeb(*buf++, addr);
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} while (--count);
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}
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}
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#endif
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#ifndef writesw
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#define writesw writesw
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static inline void writesw(volatile void __iomem *addr, const void *buffer,
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unsigned int count)
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{
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if (count) {
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const u16 *buf = buffer;
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do {
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__raw_writew(*buf++, addr);
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} while (--count);
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}
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}
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#endif
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#ifndef writesl
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#define writesl writesl
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static inline void writesl(volatile void __iomem *addr, const void *buffer,
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unsigned int count)
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{
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if (count) {
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const u32 *buf = buffer;
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do {
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__raw_writel(*buf++, addr);
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} while (--count);
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}
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}
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#endif
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#ifndef writesq
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#define writesq writesq
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static inline void writesq(volatile void __iomem *addr, const void *buffer,
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unsigned int count)
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{
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if (count) {
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const u64 *buf = buffer;
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do {
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__raw_writeq(*buf++, addr);
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} while (--count);
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}
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||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TOOLS_ASM_GENERIC_IO_H */
|
||||
7
tools/include/asm/io.h
Normal file
7
tools/include/asm/io.h
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _TOOLS_ASM_IO_H
|
||||
#define _TOOLS_ASM_IO_H
|
||||
|
||||
#include <asm-generic/io.h>
|
||||
|
||||
#endif /* _TOOLS_ASM_IO_H */
|
||||
|
|
@ -2,4 +2,6 @@
|
|||
#ifndef _TOOLS_IO_H
|
||||
#define _TOOLS_IO_H
|
||||
|
||||
#endif
|
||||
#include <asm/io.h>
|
||||
|
||||
#endif /* _TOOLS_IO_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue