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dt-bindings: Changes for v6.20-rc1

Browse source 
This series updates various DT bindings for Tegra architecture,
 primarily focusing on schema validation fixes and new feature
 documentation for Tegra234 and Tegra264 SoCs. Key changes include
 converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and
 IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock
 support). Additionally, it resolves legacy warnings for Tegra30/132
 display and VI interfaces.
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Merge tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

dt-bindings: Changes for v6.20-rc1

This series updates various DT bindings for Tegra architecture,
primarily focusing on schema validation fixes and new feature
documentation for Tegra234 and Tegra264 SoCs. Key changes include
converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and
IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock
support). Additionally, it resolves legacy warnings for Tegra30/132
display and VI interfaces.

* tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: display: tegra: document Tegra30 VI and VIP
  dt-bindings: display: tegra: document Tegra132 MIPI calibration device
  dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema
  dt-bindings: dma: Update ADMA bindings for tegra264
  dt-bindings: iommu: Add NVIDIA Tegra CMDQV support
  dt-bindings: memory: tegra: Document DBB clock for Tegra264
  dt-bindings: tegra: pmc: Update aotag as an optional aperture
This commit is contained in:
Arnd Bergmann 2026-01-28 16:56:11 +01:00
commit 1daa947cb2
11 changed files with 225 additions and 80 deletions
Download patch file Download diff file Expand all files Collapse all files

11
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
View file

@ -19,15 +19,15 @@ properties:
- nvidia,tegra264-pmc
reg:
minItems: 4
minItems: 3
maxItems: 5
reg-names:
minItems: 4
minItems: 3
items:
- const: pmc
- const: wake
- const: aotag
- enum: [ aotag, scratch, misc ]
- enum: [ scratch, misc ]
- const: misc
@ -51,6 +51,7 @@ allOf:
then:
properties:
reg:
minItems: 4
maxItems: 4
reg-names:
maxItems: 4
@ -73,7 +74,9 @@ allOf:
properties:
compatible:
contains:
const: nvidia,tegra234-pmc
enum:
- nvidia,tegra234-pmc
- nvidia,tegra264-pmc
then:
properties:
reg-names:

1
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
View file

@ -18,6 +18,7 @@ properties:
enum:
- nvidia,tegra114-mipi
- nvidia,tegra124-mipi
- nvidia,tegra132-mipi
- nvidia,tegra210-mipi
- nvidia,tegra186-mipi

19
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
View file

@ -16,16 +16,21 @@ properties:
compatible:
oneOf:
- const: nvidia,tegra20-vi
- const: nvidia,tegra30-vi
- const: nvidia,tegra114-vi
- const: nvidia,tegra124-vi
- enum:
- nvidia,tegra20-vi
- nvidia,tegra114-vi
- nvidia,tegra124-vi
- nvidia,tegra210-vi
- nvidia,tegra186-vi
- nvidia,tegra194-vi
- items:
- const: nvidia,tegra30-vi
- const: nvidia,tegra20-vi
- items:
- const: nvidia,tegra132-vi
- const: nvidia,tegra124-vi
- const: nvidia,tegra210-vi
- const: nvidia,tegra186-vi
- const: nvidia,tegra194-vi
reg:
maxItems: 1

9
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml
View file

@ -11,8 +11,13 @@ maintainers:
properties:
compatible:
enum:
- nvidia,tegra20-vip
oneOf:
- enum:
- nvidia,tegra20-vip
- items:
- const: nvidia,tegra30-vip
- const: nvidia,tegra20-vip
ports:
$ref: /schemas/graph.yaml#/properties/ports

15
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
View file

@ -46,7 +46,7 @@ properties:
Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
minItems: 1
maxItems: 32
maxItems: 64
clocks:
description: Must contain one entry for the ADMA module clock
@ -86,6 +86,19 @@ allOf:
reg:
items:
- description: Full address space range of DMA registers.
interrupts:
maxItems: 22
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra186-adma
then:
properties:
interrupts:
maxItems: 32
- if:
properties:

27
Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
View file

@ -20,7 +20,12 @@ properties:
$nodename:
pattern: "^iommu@[0-9a-f]*"
compatible:
const: arm,smmu-v3
oneOf:
- const: arm,smmu-v3
- items:
- enum:
- nvidia,tegra264-smmu
- const: arm,smmu-v3
reg:
maxItems: 1
@ -58,6 +63,15 @@ properties:
msi-parent: true
nvidia,cmdqv:
description: |
A phandle to its pairing CMDQV extension for an implementation on NVIDIA
Tegra SoC.
If this property is absent, CMDQ-Virtualization won't be used and SMMU
will only use its own CMDQ.
$ref: /schemas/types.yaml#/definitions/phandle
hisilicon,broken-prefetch-cmd:
type: boolean
description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
@ -69,6 +83,17 @@ properties:
register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
doesn't support SMMU page1 register space.
allOf:
- if:
not:
properties:
compatible:
contains:
const: nvidia,tegra264-smmu
then:
properties:
nvidia,cmdqv: false
required:
- compatible
- reg

42
Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml Normal file
View file

@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra264 CMDQV
description:
The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
maintainers:
- Nicolin Chen <nicolinc@nvidia.com>
properties:
compatible:
const: nvidia,tegra264-cmdqv
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
cmdqv@5200000 {
compatible = "nvidia,tegra264-cmdqv";
reg = <0x5200000 0x830000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
};

13
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
View file

@ -92,10 +92,14 @@ patternProperties:
clocks:
items:
- description: external memory clock
- description: data backbone clock
minItems: 1
clock-names:
items:
- const: emc
- const: dbb
minItems: 1
"#interconnect-cells":
const: 0
@ -115,6 +119,9 @@ patternProperties:
reg:
maxItems: 1
clocks:
maxItems: 1
- if:
properties:
compatible:
@ -124,6 +131,9 @@ patternProperties:
reg:
minItems: 2
clocks:
maxItems: 1
- if:
properties:
compatible:
@ -133,6 +143,9 @@ patternProperties:
reg:
minItems: 2
clocks:
maxItems: 1
- if:
properties:
compatible:

102
Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml Normal file
View file

@ -0,0 +1,102 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NAND Flash Controller
maintainers:
- Jonathan Hunter <jonathanh@nvidia.com>
allOf:
- $ref: nand-controller.yaml
description:
The NVIDIA NAND controller provides an interface between NVIDIA SoCs
and raw NAND flash devices. It supports standard NAND operations,
hardware-assisted ECC, OOB data access, and DMA transfers, and
integrates with the Linux MTD NAND subsystem for reliable flash management.
properties:
compatible:
const: nvidia,tegra20-nand
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nand
resets:
maxItems: 1
reset-names:
items:
- const: nand
power-domains:
maxItems: 1
operating-points-v2:
maxItems: 1
patternProperties:
'^nand@':
type: object
description: Individual NAND chip connected to the NAND controller
$ref: raw-nand-chip.yaml#
properties:
reg:
maximum: 5
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
nand-controller@70008000 {
compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
clock-names = "nand";
resets = <&tegra_car 13>;
reset-names = "nand";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-bus-width = <8>;
nand-on-flash-bbt;
nand-ecc-algo = "bch";
nand-ecc-strength = <8>;
wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
};
};
...

64
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
View file

@ -1,64 +0,0 @@
NVIDIA Tegra NAND Flash controller
Required properties:
- compatible: Must be one of:
- "nvidia,tegra20-nand"
- reg: MMIO address range
- interrupts: interrupt output of the NFC controller
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- nand
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- nand
Optional children nodes:
Individual NAND chips are children of the NAND controller node. Currently
only one NAND chip supported.
Required children node properties:
- reg: An integer ranging from 1 to 6 representing the CS line to use.
Optional children node properties:
- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
"hw" is supported.
- nand-ecc-algo: string, algorithm of NAND ECC.
Supported values with "hw" ECC mode are: "rs", "bch".
- nand-bus-width : See nand-controller.yaml
- nand-on-flash-bbt: See nand-controller.yaml
- nand-ecc-strength: integer representing the number of bits to correct
per ECC step (always 512). Supported strength using HW ECC
modes are:
- RS: 4, 6, 8
- BCH: 4, 8, 14, 16
- nand-ecc-maximize: See nand-controller.yaml
- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
are chosen.
- wp-gpios: GPIO specifier for the write protect pin.
Optional child node of NAND chip nodes:
Partitions: see mtd.yaml
Example:
nand-controller@70008000 {
compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
clock-names = "nand";
resets = <&tegra_car 13>;
reset-names = "nand";
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-bus-width = <8>;
nand-on-flash-bbt;
nand-ecc-algo = "bch";
nand-ecc-strength = <8>;
wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
};
};

2
MAINTAINERS
View file

@ -25677,7 +25677,7 @@ TEGRA NAND DRIVER
M: Stefan Agner <stefan@agner.ch>
M: Lucas Stach <dev@lynxeye.de>
S: Maintained
F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml
F: drivers/mtd/nand/raw/tegra_nand.c
TEGRA PWM DRIVER