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drm/amd/display: add 3D LUT colorop
This adds support for a 3D LUT. The color pipeline now consists of the following colorops: 1. 1D curve colorop 2. Multiplier 3. 3x4 CTM 4. 1D curve colorop 5. 1D LUT 6. 3D LUT 7. 1D curve colorop 8. 1D LUT Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Simon Ser <contact@emersion.fr> Link: https://patch.msgid.link/20251115000237.3561250-47-alex.hung@amd.com
This commit is contained in:
Alex Hung
Simon Ser
parent
db971856bb
commit
0de2b1afea
2 changed files with 175 additions and 0 deletions
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@ -866,6 +866,59 @@ static void __drm_3dlut_to_dc_3dlut(const struct drm_color_lut *lut,
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__to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth);
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}
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static void __to_dc_lut3d_32_color(struct dc_rgb *rgb,
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const struct drm_color_lut32 lut,
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int bit_precision)
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{
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rgb->red = drm_color_lut32_extract(lut.red, bit_precision);
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rgb->green = drm_color_lut32_extract(lut.green, bit_precision);
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rgb->blue = drm_color_lut32_extract(lut.blue, bit_precision);
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}
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static void __drm_3dlut32_to_dc_3dlut(const struct drm_color_lut32 *lut,
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uint32_t lut3d_size,
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struct tetrahedral_params *params,
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bool use_tetrahedral_9,
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int bit_depth)
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{
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struct dc_rgb *lut0;
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struct dc_rgb *lut1;
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struct dc_rgb *lut2;
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struct dc_rgb *lut3;
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int lut_i, i;
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if (use_tetrahedral_9) {
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lut0 = params->tetrahedral_9.lut0;
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lut1 = params->tetrahedral_9.lut1;
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lut2 = params->tetrahedral_9.lut2;
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lut3 = params->tetrahedral_9.lut3;
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} else {
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lut0 = params->tetrahedral_17.lut0;
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lut1 = params->tetrahedral_17.lut1;
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lut2 = params->tetrahedral_17.lut2;
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lut3 = params->tetrahedral_17.lut3;
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}
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for (lut_i = 0, i = 0; i < lut3d_size - 4; lut_i++, i += 4) {
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/*
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* We should consider the 3D LUT RGB values are distributed
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* along four arrays lut0-3 where the first sizes 1229 and the
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* other 1228. The bit depth supported for 3dlut channel is
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* 12-bit, but DC also supports 10-bit.
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*
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* TODO: improve color pipeline API to enable the userspace set
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* bit depth and 3D LUT size/stride, as specified by VA-API.
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*/
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__to_dc_lut3d_32_color(&lut0[lut_i], lut[i], bit_depth);
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__to_dc_lut3d_32_color(&lut1[lut_i], lut[i + 1], bit_depth);
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__to_dc_lut3d_32_color(&lut2[lut_i], lut[i + 2], bit_depth);
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__to_dc_lut3d_32_color(&lut3[lut_i], lut[i + 3], bit_depth);
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}
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/* lut0 has 1229 points (lut_size/4 + 1) */
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__to_dc_lut3d_32_color(&lut0[lut_i], lut[i], bit_depth);
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}
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/* amdgpu_dm_atomic_lut3d - set DRM 3D LUT to DC stream
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* @drm_lut3d: user 3D LUT
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* @drm_lut3d_size: size of 3D LUT
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@ -1460,6 +1513,7 @@ __set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state,
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struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func;
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const struct drm_color_lut32 *shaper_lut;
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struct drm_device *dev = colorop->dev;
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bool enabled = false;
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u32 shaper_size;
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int i = 0, ret = 0;
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@ -1481,6 +1535,7 @@ __set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state,
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ret = __set_output_tf(tf, 0, 0, false);
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if (ret)
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return ret;
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enabled = true;
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}
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/* 1D LUT - SHAPER LUT */
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@ -1512,12 +1567,102 @@ __set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state,
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ret = __set_output_tf_32(tf, shaper_lut, shaper_size, false);
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if (ret)
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return ret;
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enabled = true;
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}
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}
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if (!enabled)
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tf->type = TF_TYPE_BYPASS;
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return 0;
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}
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/* __set_colorop_3dlut - set DRM 3D LUT to DC stream
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* @drm_lut3d: user 3D LUT
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* @drm_lut3d_size: size of 3D LUT
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* @lut3d: DC 3D LUT
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*
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* Map user 3D LUT data to DC 3D LUT and all necessary bits to program it
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* on DCN accordingly.
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*
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* Returns:
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* 0 on success. -EINVAL if drm_lut3d_size is zero.
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*/
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static int __set_colorop_3dlut(const struct drm_color_lut32 *drm_lut3d,
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uint32_t drm_lut3d_size,
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struct dc_3dlut *lut)
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{
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if (!drm_lut3d_size) {
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lut->state.bits.initialized = 0;
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return -EINVAL;
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}
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/* Only supports 17x17x17 3D LUT (12-bit) now */
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lut->lut_3d.use_12bits = true;
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lut->lut_3d.use_tetrahedral_9 = false;
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lut->state.bits.initialized = 1;
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__drm_3dlut32_to_dc_3dlut(drm_lut3d, drm_lut3d_size, &lut->lut_3d,
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lut->lut_3d.use_tetrahedral_9, 12);
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return 0;
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}
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static int
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__set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state,
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struct dc_plane_state *dc_plane_state,
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struct drm_colorop *colorop)
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{
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struct drm_colorop *old_colorop;
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struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;
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struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func;
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struct drm_atomic_state *state = plane_state->state;
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const struct amdgpu_device *adev = drm_to_adev(colorop->dev);
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const struct drm_device *dev = colorop->dev;
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const struct drm_color_lut32 *lut3d;
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uint32_t lut3d_size;
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int i = 0, ret = 0;
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/* 3D LUT */
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old_colorop = colorop;
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for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
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if (new_colorop_state->colorop == old_colorop &&
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new_colorop_state->colorop->type == DRM_COLOROP_3D_LUT) {
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colorop_state = new_colorop_state;
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break;
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}
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}
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if (colorop_state && !colorop_state->bypass && colorop->type == DRM_COLOROP_3D_LUT) {
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if (!adev->dm.dc->caps.color.dpp.hw_3d_lut) {
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drm_dbg(dev, "3D LUT is not supported by hardware\n");
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return -EINVAL;
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}
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drm_dbg(dev, "3D LUT colorop with ID: %d\n", colorop->base.id);
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lut3d = __extract_blob_lut32(colorop_state->data, &lut3d_size);
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lut3d_size = lut3d != NULL ? lut3d_size : 0;
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ret = __set_colorop_3dlut(lut3d, lut3d_size, &dc_plane_state->lut3d_func);
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if (ret) {
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drm_dbg(dev, "3D LUT colorop with ID: %d has LUT size = %d\n",
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colorop->base.id, lut3d_size);
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return ret;
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}
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/* 3D LUT requires shaper. If shaper colorop is bypassed, enable shaper curve
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* with TRANSFER_FUNCTION_LINEAR
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*/
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if (tf->type == TF_TYPE_BYPASS) {
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tf->type = TF_TYPE_DISTRIBUTED_POINTS;
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tf->tf = TRANSFER_FUNCTION_LINEAR;
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tf->sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;
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ret = __set_output_tf_32(tf, NULL, 0, false);
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}
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}
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return ret;
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}
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static int
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__set_dm_plane_colorop_blend(struct drm_plane_state *plane_state,
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struct dc_plane_state *dc_plane_state,
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@ -1689,6 +1834,17 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,
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if (!colorop)
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return -EINVAL;
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/* 3D LUT */
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colorop = colorop->next;
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if (!colorop) {
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drm_dbg(dev, "no 3D LUT colorop found\n");
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return -EINVAL;
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}
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ret = __set_dm_plane_colorop_3dlut(plane_state, dc_plane_state, colorop);
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if (ret)
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return ret;
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/* 1D Curve & LUT - BLND TF & LUT */
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colorop = colorop->next;
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if (!colorop) {
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@ -49,6 +49,8 @@ const u64 amdgpu_dm_supported_blnd_tfs =
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#define MAX_COLOR_PIPELINE_OPS 10
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#define LUT3D_SIZE 17
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int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list)
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{
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struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS];
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@ -140,6 +142,23 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr
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i++;
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/* 3D LUT */
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ops[i] = kzalloc(sizeof(struct drm_colorop), GFP_KERNEL);
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if (!ops[i]) {
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ret = -ENOMEM;
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goto cleanup;
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}
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ret = drm_plane_colorop_3dlut_init(dev, ops[i], plane, LUT3D_SIZE,
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DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
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DRM_COLOROP_FLAG_ALLOW_BYPASS);
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if (ret)
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goto cleanup;
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drm_colorop_set_next_property(ops[i-1], ops[i]);
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i++;
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/* 1D curve - BLND TF */
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ops[i] = kzalloc(sizeof(*ops[0]), GFP_KERNEL);
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if (!ops[i]) {
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