archives/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-03-08 03:24:45 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

soc: fixes for 6.15, part 2

Browse source 
These all address issues in devicetree files:
 
 - The Rockchip rk3588j are now limited the same way as the vendor
   kernel, to allow room for the industrial-grade temperature
   ranges.
 
 - Seven more Rockchip fixes address minor issues with
   specific boards
 
 - Invalid clk controller references in multiple amlogic
   chips, plus one accidentally disabled audio on clock
 
 - Two devicetree fixes for i.MX8MP boards, both for incorrect
   regulator settings
 
 - A power domain change for apple laptop touchbar, fixing
   suspend/resume problems
 
 - An incorrect DMA controller setting for sophgo cv18xx
   chips
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmgiDwMACgkQYKtH/8kJ
 UieeRxAAkhvsKz8wnm83cB/BK8VCAA5LlVO2hPAyh3G1FENUsePSunOE/NymZgtp
 9a6y/SVx518NIGT2OSYEb+9qGTpTpcxBvGXOmA3x7XbIf5uCWed6d1uOmHUYgMJv
 3P4/kb2zcI9piU4oYe0pnpDLfaQW8Dn1ac5pL2Cl6N/ZOdwKnTE7TMepiWxx51gV
 C/X/GMVWfhMAH00Wxv2nc9Ky8JDLmzsst+hfR+u/yq1430B9OJorNagsuBTPV1Ys
 ZQ0gj1zM0gBCke0L0S+IpmZPWEiU7N/SMs2kGMJ+LbUCcJJfoPkqSymmBgQT2k7f
 JxIkK+qit/wVPV1+LAaXj1heRgiTWTQYC6OCkr8hQatO7w8G2OSCwWVAdC5PXHzU
 YJ+1mwK6lkD1XKCVOYvJqcaEZnKEjWImicGluaAUikkqV+uJ5M3+JyD44x+wxgxV
 kC/yHFq3NkENXI5UPpxVrbXHHfgZQ/7nlKpO4qC6E3RmwpMYy9i/PwdBBqe7/VQN
 TRcdhXWLnE+rXn5JbiB0Vzj42Qkbdj/hxeFkAWqsHXfMFvZ87ZLB+YONPmIOkxIs
 ZjZFD3UQsxcyiMIeS0PYEB/MNA/vSXU5e03krIgBvjgyQBxYQuZ6NR11mTTM8WDL
 H4KYOu5uYUTMDUTr4LM+mrDdAgd+sFwaGO6MRMoa5t5Izc5K8oc=
 =6PRF
 -----END PGP SIGNATURE-----

Merge tag 'soc-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC fixes from Arnd Bergmann:
 "These all address issues in devicetree files:

   - The Rockchip rk3588j are now limited the same way as the vendor
     kernel, to allow room for the industrial-grade temperature ranges.

   - Seven more Rockchip fixes address minor issues with specific boards

   - Invalid clk controller references in multiple amlogic chips, plus
     one accidentally disabled audio on clock

   - Two devicetree fixes for i.MX8MP boards, both for incorrect
     regulator settings

   - A power domain change for apple laptop touchbar, fixing
     suspend/resume problems

   - An incorrect DMA controller setting for sophgo cv18xx chips"

* tag 'soc-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  arm64: dts: amazon: Fix simple-bus node name schema warnings
  MAINTAINERS: delete email for Shiraz Hashim
  arm64: dts: imx8mp-var-som: Fix LDO5 shutdown causing SD card timeout
  arm64: dts: imx8mp: use 800MHz NoC OPP for nominal drive mode
  arm64: dts: amlogic: dreambox: fix missing clkc_audio node
  riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
  arm64: dts: rockchip: fix Sige5 RTC interrupt pin
  arm64: dts: rockchip: Assign RT5616 MCLK rate on rk3588-friendlyelec-cm3588
  arm64: dts: rockchip: Align wifi node name with bindings in CB2
  arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock
  arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock
  ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clock
  ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock
  arm64: dts: apple: touchbar: Mark ps_dispdfr_be as always-on
  mailmap: Update email for Asahi Lina
  arm64: dts: rockchip: Fix mmc-pwrseq clock name on rock-pi-4
  arm64: dts: rockchip: Use "regulator-fixed" for btreg on px30-engicam for vcc3v3-btreg
  arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433
  arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsi
  arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin down
This commit is contained in:
Linus Torvalds 2025-05-14 09:11:05 -07:00
commit 00f281fd9d
26 changed files with 93 additions and 63 deletions
Download patch file Download diff file Expand all files Collapse all files

1
.mailmap
View file

@ -102,6 +102,7 @@ Ard Biesheuvel <ardb@kernel.org> <ard.biesheuvel@linaro.org>
Arnaud Patard <arnaud.patard@rtp-net.org>
Arnd Bergmann <arnd@arndb.de>
Arun Kumar Neelakantam <quic_aneela@quicinc.com> <aneela@codeaurora.org>
Asahi Lina <lina+kernel@asahilina.net> <lina@asahilina.net>
Ashok Raj Nagarajan <quic_arnagara@quicinc.com> <arnagara@codeaurora.org>
Ashwin Chaugule <quic_ashwinc@quicinc.com> <ashwinc@codeaurora.org>
Asutosh Das <quic_asutoshd@quicinc.com> <asutoshd@codeaurora.org>

1
MAINTAINERS
View file

@ -22916,7 +22916,6 @@ F: drivers/accessibility/speakup/
SPEAR PLATFORM/CLOCK/PINCTRL SUPPORT
M: Viresh Kumar <vireshk@kernel.org>
M: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: soc@lists.linux.dev
S: Maintained

6
arch/arm/boot/dts/amlogic/meson8.dtsi
View file

@ -451,7 +451,7 @@
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<0>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
reg = <0x86c0 0x10>;
@ -705,7 +705,7 @@
&pwm_ab {
compatible = "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<0>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
@ -713,7 +713,7 @@
&pwm_cd {
compatible = "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<0>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};

6
arch/arm/boot/dts/amlogic/meson8b.dtsi
View file

@ -406,7 +406,7 @@
compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
reg = <0x86c0 0x10>;
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<0>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
#pwm-cells = <3>;
@ -680,7 +680,7 @@
&pwm_ab {
compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<0>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
@ -688,7 +688,7 @@
&pwm_cd {
compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<0>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};

2
arch/arm64/boot/dts/amazon/alpine-v2.dtsi
View file

@ -151,7 +151,7 @@
al,msi-num-spis = <160>;
};
io-fabric@fc000000 {
io-bus@fc000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm64/boot/dts/amazon/alpine-v3.dtsi
View file

@ -361,7 +361,7 @@
interrupt-parent = <&gic>;
};
io-fabric@fc000000 {
io-bus@fc000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

6
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View file

@ -2313,7 +2313,7 @@
"amlogic,meson8-pwm-v2";
reg = <0x0 0x19000 0x0 0x20>;
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
#pwm-cells = <3>;
@ -2325,7 +2325,7 @@
"amlogic,meson8-pwm-v2";
reg = <0x0 0x1a000 0x0 0x20>;
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
#pwm-cells = <3>;
@ -2337,7 +2337,7 @@
"amlogic,meson8-pwm-v2";
reg = <0x0 0x1b000 0x0 0x20>;
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
#pwm-cells = <3>;

4
arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi
View file

@ -116,6 +116,10 @@
status = "okay";
};
&clkc_audio {
status = "okay";
};
&frddr_a {
status = "okay";
};

6
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View file

@ -741,7 +741,7 @@
&pwm_ab {
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
@ -752,14 +752,14 @@
&pwm_cd {
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
&pwm_ef {
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};

6
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View file

@ -811,7 +811,7 @@
&pwm_ab {
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
@ -822,14 +822,14 @@
&pwm_cd {
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
&pwm_ef {
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};

10
arch/arm64/boot/dts/apple/t8103-j293.dts
View file

@ -77,6 +77,16 @@
};
};
/*
* The driver depends on boot loader initialized state which resets when this
* power-domain is powered off. This happens on suspend or when the driver is
* missing during boot. Mark the domain as always on until the driver can
* handle this.
*/
&ps_dispdfr_be {
apple,always-on;
};
&display_dfr {
status = "okay";
};

10
arch/arm64/boot/dts/apple/t8112-j493.dts
View file

@ -40,6 +40,16 @@
};
};
/*
* The driver depends on boot loader initialized state which resets when this
* power-domain is powered off. This happens on suspend or when the driver is
* missing during boot. Mark the domain as always on until the driver can
* handle this.
*/
&ps_dispdfr_be {
apple,always-on;
};
&display_dfr {
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi
View file

@ -88,3 +88,5 @@
<0>, <0>, <400000000>,
<1039500000>;
};
/delete-node/ &{noc_opp_table/opp-1000000000};

12
arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
View file

@ -35,7 +35,6 @@
<0x1 0x00000000 0 0xc0000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
@ -46,6 +45,16 @@
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
compatible = "regulator-gpio";
regulator-name = "VSD_VSEL";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
states = <3300000 0x0 1800000 0x1>;
vin-supply = <&ldo5>;
};
};
&A53_0 {
@ -205,6 +214,7 @@
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_usdhc2_vqmmc>;
bus-width = <4>;
status = "okay";
};

6
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View file

@ -1645,6 +1645,12 @@
opp-hz = /bits/ 64 <200000000>;
};
/* Nominal drive mode maximum */
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
/* Overdrive mode maximum */
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
};

3
arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
View file

@ -31,7 +31,7 @@
};
vcc3v3_btreg: vcc3v3-btreg {
compatible = "regulator-gpio";
compatible = "regulator-fixed";
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&bt_enable_h>;
@ -39,7 +39,6 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
states = <3300000 0x0>;
};
vcc3v3_rf_aux_mod: regulator-vcc3v3-rf-aux-mod {

2
arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
View file

@ -26,5 +26,5 @@
};
&vcc3v3_btreg {
enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
};

2
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
View file

@ -39,5 +39,5 @@
};
&vcc3v3_btreg {
enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
};

2
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
View file

@ -43,7 +43,7 @@
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "lpo";
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;

2
arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi
View file

@ -775,7 +775,7 @@
rockchip,default-sample-phase = <90>;
status = "okay";
sdio-wifi@1 {
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;

2
arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
View file

@ -619,6 +619,8 @@
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
status = "okay";
};

2
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
View file

@ -610,7 +610,7 @@
reg = <0x51>;
clock-output-names = "hym8563";
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
wakeup-source;

4
arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
View file

@ -222,6 +222,10 @@
compatible = "realtek,rt5616";
reg = <0x1b>;
#sound-dai-cells = <0>;
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
clock-names = "mclk";
};
};

2
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
View file

@ -214,6 +214,8 @@
};
&package_thermal {
polling-delay = <1000>;
trips {
package_active1: trip-active1 {
temperature = <45000>;

53
arch/arm64/boot/dts/rockchip/rk3588j.dtsi
View file

@ -11,20 +11,15 @@
compatible = "operating-points-v2";
opp-shared;
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <887500 887500 950000>;
clock-latency-ns = <40000>;
};
opp-1704000000 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <937500 937500 950000>;
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <775000 775000 950000>;
clock-latency-ns = <40000>;
};
};
@ -33,9 +28,14 @@
compatible = "operating-points-v2";
opp-shared;
opp-1200000000{
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <750000 750000 950000>;
opp-microvolt = <762500 762500 950000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
@ -43,25 +43,20 @@
opp-microvolt = <787500 787500 950000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <875000 875000 950000>;
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <950000 950000 950000>;
clock-latency-ns = <40000>;
};
};
cluster2_opp_table: opp-table-cluster2 {
compatible = "operating-points-v2";
opp-shared;
opp-1200000000{
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <750000 750000 950000>;
opp-microvolt = <762500 762500 950000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
@ -69,16 +64,6 @@
opp-microvolt = <787500 787500 950000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <875000 875000 950000>;
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <950000 950000 950000>;
clock-latency-ns = <40000>;
};
};
gpu_opp_table: opp-table {
@ -104,10 +89,6 @@
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <750000 750000 850000>;
};
opp-850000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <787500 787500 850000>;
};
};
};

2
arch/riscv/boot/dts/sophgo/cv18xx.dtsi
View file

@ -341,7 +341,7 @@
1024 1024 1024 1024>;
snps,priority = <0 1 2 3 4 5 6 7>;
snps,dma-masters = <2>;
snps,data-width = <4>;
snps,data-width = <2>;
status = "disabled";
};